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Tue, 08 Sep 2026 10:44:36 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 6/8] dt-bindings: reset: Add mmsys reset ids for mt8167 Date: Tue, 8 Sep 2026 19:38:33 +0200 Message-ID: <20260908174259.9009-7-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908174259.9009-1-l.scorcia@gmail.com> References: <20260908174259.9009-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit According to the SoC data sheet mt8167 has 28 mmsys resets. Add the IDs that can be used in device trees to identify subsystem resets. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- .../dt-bindings/reset/mediatek,mt8167-mmsys.h | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt8167-mmsys.h diff --git a/include/dt-bindings/reset/mediatek,mt8167-mmsys.h b/include/dt-bindings/reset/mediatek,mt8167-mmsys.h new file mode 100644 index 000000000000..b21f67b3b55c --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8167-mmsys.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +#ifndef _DT_BINDINGS_RESET_MEDIATEK_MT8167_MMSYS_H_ +#define _DT_BINDINGS_RESET_MEDIATEK_MT8167_MMSYS_H_ + +/* MMSYS reset IDs */ +#define MT8167_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT8167_MMSYS_SW0_RST_B_SMI_LARB0 1 +#define MT8167_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT8167_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ0 4 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ1 5 +#define MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0 6 +#define MT8167_MMSYS_SW0_RST_B_MDP_WDMA 7 +#define MT8167_MMSYS_SW0_RST_B_MDP_WROT0 8 +#define MT8167_MMSYS_SW0_RST_B_FAKE_ENG 9 +#define MT8167_MMSYS_SW0_RST_B_MUTEX 10 +#define MT8167_MMSYS_SW0_RST_B_DISP_OVL0 11 +#define MT8167_MMSYS_SW0_RST_B_DISP_RDMA0 12 +#define MT8167_MMSYS_SW0_RST_B_DISP_RDMA1 13 +#define MT8167_MMSYS_SW0_RST_B_DISP_WDMA0 14 +#define MT8167_MMSYS_SW0_RST_B_DISP_COLOR 15 +#define MT8167_MMSYS_SW0_RST_B_DISP_CCORR 16 +#define MT8167_MMSYS_SW0_RST_B_DISP_AAL 17 +#define MT8167_MMSYS_SW0_RST_B_DISP_GAMMA 18 +#define MT8167_MMSYS_SW0_RST_B_DISP_DITHER 19 +#define MT8167_MMSYS_SW0_RST_B_DISP_UFOE 20 +#define MT8167_MMSYS_SW0_RST_B_DISP_PWM 21 +#define MT8167_MMSYS_SW0_RST_B_DSI0 22 +#define MT8167_MMSYS_SW0_RST_B_DPI0 23 +#define MT8167_MMSYS_SW0_RST_B_MIPI_TX_CONFIG 24 +#define MT8167_MMSYS_SW1_RST_B_LVDS_ENCODER 25 +#define MT8167_MMSYS_SW1_RST_B_DPI1 26 +#define MT8167_MMSYS_SW1_RST_B_HDMI 27 + +#endif /* _DT_BINDINGS_RESET_MEDIATEK_MT8167_MMSYS_H_ */ -- 2.43.0