Linux Watchdog driver development
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From: sashiko-bot@kernel.org
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: wsa+renesas@sang-engineering.com, conor+dt@kernel.org,
	devicetree@vger.kernel.org, robh@kernel.org,
	linux-clk@vger.kernel.org, linux-watchdog@vger.kernel.org
Subject: Re: [PATCH v7 3/8] watchdog: rzv2h: Drop enabling clocks in the restart handler
Date: Tue, 29 Sep 2026 11:06:02 +0000	[thread overview]
Message-ID: <20260929110602.D533D1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260929105021.542730-4-prabhakar.mahadev-lad.rj@bp.renesas.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] watchdog: unintended system reset during suspend due to permanently enabled clocks
--

commit 465743d35253a3a281f9ce8cea373ed0c3ae3e5a
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

watchdog: rzv2h: Drop enabling clocks in the restart handler
    
The commit drops dynamic clock enable/disable operations from the watchdog
restart handler to avoid deadlocking on the clock framework's global
enable_lock. Instead, it keeps the peripheral and oscillator clocks enabled
for the lifetime of the device using devm_clk_get_enabled() and
devm_clk_get_optional_enabled().

> diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
> index f247e42d54f54..55ac11fcfcabd 100644
> --- a/drivers/watchdog/rzv2h_wdt.c
> +++ b/drivers/watchdog/rzv2h_wdt.c

[ ... ]

> @@ -292,11 +279,11 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
>  	if (IS_ERR(priv->base))
>  		return PTR_ERR(priv->base);
>  
> -	priv->pclk = devm_clk_get_prepared(dev, "pclk");
> +	priv->pclk = devm_clk_get_enabled(dev, "pclk");
>  	if (IS_ERR(priv->pclk))
>  		return dev_err_probe(dev, PTR_ERR(priv->pclk), "Failed to get pclk\n");
>  
> -	priv->oscclk = devm_clk_get_optional_prepared(dev, "oscclk");
> +	priv->oscclk = devm_clk_get_optional_enabled(dev, "oscclk");

[Severity: High]
Does switching to devm_clk_get_enabled() and devm_clk_get_optional_enabled()
prevent the PM framework from fully gating these clocks during suspend?

By permanently incrementing the CCF enable_count by 1 here in probe, it appears
that pm_clk_suspend() will only drop the count from 2 to 1 during system
suspend, leaving the clocks physically enabled.

If the clocks remain running while the system is suspended and the ping worker
is frozen, won't the hardware watchdog counter inevitably underflow and trigger
an unintended system reset?

>  	if (IS_ERR(priv->oscclk))
>  		return dev_err_probe(dev, PTR_ERR(priv->oscclk), "Failed to get oscclk\n");
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260929105021.542730-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=3

  reply	other threads:[~2026-09-29 11:06 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-29 10:50 [PATCH v7 0/8] Add syscon support for Renesas WDT driver Prabhakar
2026-09-29 10:50 ` [PATCH v7 1/8] clk: renesas: r9a09g077: Add helper to start WDTDCR counter Prabhakar
2026-09-29 10:50 ` [PATCH v7 2/8] watchdog: rzv2h: Use pm_runtime_put_sync() Prabhakar
2026-09-29 10:50 ` [PATCH v7 3/8] watchdog: rzv2h: Drop enabling clocks in the restart handler Prabhakar
2026-09-29 11:06   ` sashiko-bot [this message]
2026-09-30  8:36     ` Lad, Prabhakar
2026-09-29 10:50 ` [PATCH v7 4/8] watchdog: rzv2h: Drop WDTRCR_RSTIRQS define Prabhakar
2026-09-29 10:50 ` [PATCH v7 5/8] watchdog: rzv2h: Drop runtime PM handling from WDTDCR init Prabhakar
2026-09-29 10:50 ` [PATCH v7 6/8] watchdog: rzv2h_wdt: Add syscon based WDTDCR access Prabhakar
2026-09-29 10:50 ` [PATCH v7 7/8] arm64: dts: renesas: r9a09g077: Use CPG/MSSR syscon for " Prabhakar
2026-09-29 10:50 ` [PATCH v7 8/8] arm64: dts: renesas: r9a09g087: " Prabhakar
2026-09-29 11:00   ` sashiko-bot

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