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([188.243.183.76]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e25835b1dsm13621390f8f.40.2026.10.22.06.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2026 06:44:01 -0700 (PDT) From: Artem Shimko To: wim@linux-watchdog.org, linux@roeck-us.net, p.zabel@pengutronix.de, Sergey.Semin@baikalelectronics.ru, mika.westerberg@linux.intel.com, andi.shyti@kernel.org, iav@iav.lv Cc: Artem Shimko , linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] watchdog: dw_wdt: manage reset line during system suspend/resume Date: Thu, 22 Oct 2026 16:43:50 +0300 Message-ID: <20261022134354.534642-3-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261022134354.534642-1-a.shimko.dev@gmail.com> References: <20261022134354.534642-1-a.shimko.dev@gmail.com> X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The watchdog controller reset line is not currently managed during system suspend/resume. This can lead to an inconsistent hardware state when resuming from suspend, as the controller may not be properly reinitialized. Assert the reset line before disabling clocks during suspend to ensure the controller is held in reset while power is gated. During resume, deassert the reset after clocks are enabled and before restoring register state to guarantee the controller is properly initialized. Add proper error handling for reset control operations during resume with appropriate cleanup path on failure. Signed-off-by: Artem Shimko --- drivers/watchdog/dw_wdt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c index 2cffe337b4ea..ec6a09673da4 100644 --- a/drivers/watchdog/dw_wdt.c +++ b/drivers/watchdog/dw_wdt.c @@ -382,6 +382,8 @@ static int dw_wdt_suspend(struct device *dev) dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); + reset_control_assert(dw_wdt->rst); + clk_disable_unprepare(dw_wdt->pclk); clk_disable_unprepare(dw_wdt->clk); @@ -402,12 +404,22 @@ static int dw_wdt_resume(struct device *dev) return err; } + err = reset_control_deassert(dw_wdt->rst); + if (err) + goto unprepare_pclk; + writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt_ping(&dw_wdt->wdd); return 0; + +unprepare_pclk: + clk_disable_unprepare(dw_wdt->pclk); + clk_disable_unprepare(dw_wdt->clk); + + return err; } static DEFINE_SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); -- 2.43.0