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Thu, 29 Oct 2026 02:01:58 -0700 (PDT) Received: from at-Standard-PC-Q35-ICH9-2009 ([27.60.20.232]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a23641e78sm16497937eec.0.2026.10.29.02.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 02:01:58 -0700 (PDT) From: Atharva Tiwari To: Cc: Atharva Tiwari , Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , "Rafael J. Wysocki" , Len Brown , Linus Walleij , Bartosz Golaszewski , Sven Peter , Janne Grunau , Neal Gompa , Guenter Roeck , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Lee Jones , Pavel Machek , Griffin Kroah-Hartman , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Sebastian Reichel , Alexandre Belloni , Wim Van Sebroeck , Jarkko Sakkinen , Mimi Zohar , Roberto Sassu , Dmitry Kasatkin , Eric Snowberg , Paul Moore , James Morris , "Serge E. Hallyn" , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-gpio@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-hwmon@vger.kernel.org, linux-iio@vger.kernel.org, linux-leds@vger.kernel.org, mfd@lists.linux.dev, platform-driver-x86@vger.kernel.org, linux-pm@vger.kernel.org, linux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-integrity@vger.kernel.org, keyrings@vger.kernel.org, linux-security-module@vger.kernel.org Subject: [RFC PATCH 13/14] hwmon: add support for x86 macs in macsmc-hwmon Date: Thu, 29 Oct 2026 04:52:10 -0400 Message-ID: <20261029085504.3547-14-atharvatiwarilinuxdev@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261029085504.3547-1-atharvatiwarilinuxdev@gmail.com> References: <20261029085504.3547-1-atharvatiwarilinuxdev@gmail.com> X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Make macsmc-hwmon work on Intel Macs, as a replacement for the hwmon part of applesmc. Sensors now have readable names instead of raw keys like TA0P. It also adds power, current and voltage sensors that applesmc doesn't provide, and supports fan control on newer machines aswell. Signed-off-by: Atharva Tiwari --- drivers/hwmon/Kconfig | 5 +- drivers/hwmon/macsmc-hwmon.c | 816 ++++++++++++++++++++++++++++++++++- 2 files changed, 800 insertions(+), 21 deletions(-) diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 91ca7031c..4d0bb87ff 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1244,13 +1244,12 @@ config SENSORS_LTQ_CPUTEMP sensor inside your CPU. config SENSORS_MACSMC_HWMON - tristate "Apple SMC (Apple Silicon)" + tristate "Apple SMC Hardware monitoring" depends on MFD_MACSMC_CORE help This driver enables hwmon support for current, power, temperature, and voltage sensors, as well as fan speed reporting and control - on Apple Silicon devices. Say Y here if you have an Apple Silicon - device. + on Apple devices. Say Y here if you have an Apple device. This driver can also be built as a module. If so, the module will be called macsmc-hwmon. diff --git a/drivers/hwmon/macsmc-hwmon.c b/drivers/hwmon/macsmc-hwmon.c index 2e74dcd66..29e43ff4b 100644 --- a/drivers/hwmon/macsmc-hwmon.c +++ b/drivers/hwmon/macsmc-hwmon.c @@ -2,7 +2,7 @@ /* * Apple SMC hwmon driver for Apple Silicon platforms * - * The System Management Controller on Apple Silicon devices is responsible for + * The System Management Controller on Apple Silicon And Intel Macs is responsible for * measuring data from sensors across the SoC and machine. These include power, * temperature, voltage and current sensors. Some "sensors" actually expose * derived values. An example of this is the key PHPC, which is an estimate @@ -18,6 +18,11 @@ * Originally based on a concept by Jean-Francois Bortolotti * * Copyright The Asahi Linux Contributors + * + * Copyright (C) 2026 Atharva Tiwari + * + * Old macs fan control based on smcFanControl: + * Copyright (C) 2006 Hendrik Holtmann */ #include @@ -47,7 +52,7 @@ MODULE_PARM_DESC(fan_control, struct macsmc_hwmon_sensor { struct apple_smc_key_info info; smc_key macsmc_key; - char label[MAX_LABEL_LENGTH]; + char *label; u32 attrs; }; @@ -71,7 +76,8 @@ struct macsmc_hwmon_sensors { struct macsmc_hwmon_fans { struct hwmon_channel_info channel_info; struct macsmc_hwmon_fan *fans; - u32 count; + u8 count; + bool has_old_manual; }; struct macsmc_hwmon { @@ -553,8 +559,8 @@ static int macsmc_hwmon_write_f32(struct apple_smc *smc, smc_key key, long value val <<= 23 - exp; fval = FIELD_PREP(FLT_SIGN_MASK, neg) | - FIELD_PREP(FLT_EXP_MASK, exp + FLT_EXP_BIAS) | - FIELD_PREP(FLT_MANT_MASK, val & FLT_MANT_MASK); + FIELD_PREP(FLT_EXP_MASK, exp + FLT_EXP_BIAS) | + FIELD_PREP(FLT_MANT_MASK, val & FLT_MANT_MASK); } return apple_smc_write_u32(smc, key, fval); @@ -599,6 +605,23 @@ static int macsmc_hwmon_read_fan(struct macsmc_hwmon *hwmon, u32 attr, int chan, } } +static int macsmc_hwmon_write_old_fan_manual(struct macsmc_hwmon *hwmon, u8 val, int channel) +{ + int ret; + u16 buf; + + ret = apple_smc_read_u16(hwmon->smc, __SMC_KEY('F', 'S', '!', ' '), &buf); + if (ret) + return ret; + + if (val) + buf |= BIT(channel); + else + buf &= ~BIT(channel); + + return apple_smc_write_u16(hwmon->smc, __SMC_KEY('F', 'S', '!', ' '), cpu_to_be16(buf)); +} + static int macsmc_hwmon_write_fan(struct device *dev, u32 attr, int channel, long val) { @@ -606,7 +629,8 @@ static int macsmc_hwmon_write_fan(struct device *dev, u32 attr, int channel, long min, max; int ret; - if (!fan_control || hwmon->fan.fans[channel].mode.macsmc_key == 0) + if (!fan_control || (hwmon->fan.fans[channel].mode.macsmc_key == 0 && + !hwmon->fan.has_old_manual)) return -EOPNOTSUPP; /* @@ -625,7 +649,10 @@ static int macsmc_hwmon_write_fan(struct device *dev, u32 attr, int channel, if (val >= min && val <= max) { if (!hwmon->fan.fans[channel].manual) { /* Write 1 to mode key for manual control */ - ret = macsmc_hwmon_write_key(hwmon->smc, + if (hwmon->fan.has_old_manual) + ret = macsmc_hwmon_write_old_fan_manual(hwmon, 1, channel); + else + ret = macsmc_hwmon_write_key(hwmon->smc, &hwmon->fan.fans[channel].mode, 1); if (ret < 0) return ret; @@ -633,10 +660,13 @@ static int macsmc_hwmon_write_fan(struct device *dev, u32 attr, int channel, hwmon->fan.fans[channel].manual = true; } return macsmc_hwmon_write_key(hwmon->smc, - &hwmon->fan.fans[channel].set, val); + &hwmon->fan.fans[channel].set, val) > 0; } else if (!val) { if (hwmon->fan.fans[channel].manual) { - ret = macsmc_hwmon_write_key(hwmon->smc, + if (hwmon->fan.has_old_manual) + ret = macsmc_hwmon_write_old_fan_manual(hwmon, 0, channel); + else + ret = macsmc_hwmon_write_key(hwmon->smc, &hwmon->fan.fans[channel].mode, 0); if (ret < 0) return ret; @@ -697,10 +727,11 @@ static int macsmc_hwmon_write(struct device *dev, enum hwmon_sensor_types type, } static umode_t macsmc_hwmon_fan_is_visible(const struct macsmc_hwmon_fan *fan, - u32 attr) + u32 attr, bool has_old_manual) { if (fan->attrs & BIT(attr)) { - if (attr == hwmon_fan_target && fan_control && fan->mode.macsmc_key) + if (attr == hwmon_fan_target && fan_control && + (fan->mode.macsmc_key || has_old_manual)) return 0644; return 0444; @@ -710,8 +741,8 @@ static umode_t macsmc_hwmon_fan_is_visible(const struct macsmc_hwmon_fan *fan, } static umode_t macsmc_hwmon_is_visible(const void *data, - enum hwmon_sensor_types type, u32 attr, - int channel) + enum hwmon_sensor_types type, u32 attr, + int channel) { const struct macsmc_hwmon *hwmon = data; struct macsmc_hwmon_sensor *sensor; @@ -730,7 +761,8 @@ static umode_t macsmc_hwmon_is_visible(const void *data, sensor = &hwmon->temp.sensors[channel]; break; case hwmon_fan: - return macsmc_hwmon_fan_is_visible(&hwmon->fan.fans[channel], attr); + return macsmc_hwmon_fan_is_visible(&hwmon->fan.fans[channel], + attr, hwmon->fan.has_old_manual); default: return 0; } @@ -800,6 +832,578 @@ static int macsmc_hwmon_create_sensor(struct device *dev, struct apple_smc *smc, return 0; } +struct macsmc_sensor_desc { + char *name; + smc_key key; +}; + +/* + * Key's name taken from: + * https://github.com/kaiT2en/KaiT2en-Fedora/blob/main/apps/t2-smc-control/src/main.rs + * https://github.com/acidanthera/VirtualSMC/tree/master/Docs/ + */ + +static const struct macsmc_sensor_desc temp_sensors[] = { + { "Ambient 2 Raw Temperature (TA1p)", SMC_KEY(TA1p) }, + { "Ambient 3 Raw Temperature (TA2p)", SMC_KEY(TA2p) }, + { "Ambient Cooked Temperature (TA0P)", SMC_KEY(TA0P) }, + { "Ambient Cooked Temperature 1 (TA1P)", SMC_KEY(TA1P) }, + { "Ambient Cooked Temperature 2 (TA2P)", SMC_KEY(TA2P) }, + { "Ambient Raw Temperature (TA0p)", SMC_KEY(TA0p) }, + { "Ambient Virtual Temperature (TA0V)", SMC_KEY(TA0V) }, + { "Audio L Temperature (TaLC)", SMC_KEY(TaLC) }, + { "Audio R Temperature (TaRC)", SMC_KEY(TaRC) }, + { "Backlight Controller Proximity Cooked Temperature (Tb0P)", SMC_KEY(Tb0P) }, + { "Backlight Controller Proximity Raw Temperature (Tb0p)", SMC_KEY(Tb0p) }, + { "Battery Ambient Temperature (TB3T)", SMC_KEY(TB3T) }, + { "Battery Temperature (TB0T)", SMC_KEY(TB0T) }, + { "Battery Temperature, Same As TB0T (TBXT)", SMC_KEY(TBXT) }, + { "Battery TS1 Temperature (TB1T)", SMC_KEY(TB1T) }, + { "Battery TS2 Temperature (TB2T)", SMC_KEY(TB2T) }, + { "Charger Proximity Temperature (TCHP)", SMC_KEY(TCHP) }, + { "CPU 1 Heatsink Alt. Temperature (TCAH)", SMC_KEY(TCAH) }, + { "CPU 1 Heatsink Temperature (TC0H)", SMC_KEY(TC0H) }, + { "CPU 1 Package Temperature (TCAD)", SMC_KEY(TCAD) }, + { "CPU 2 Diode Filtered Temperature (TC1F)", SMC_KEY(TC1F) }, + { "CPU 2 Diode Virtual Temperature (TC1E)", SMC_KEY(TC1E) }, + { "CPU 2 Heatsink Alt. Temperature (TCBH)", SMC_KEY(TCBH) }, + { "CPU 2 Heatsink Temperature (TC1H)", SMC_KEY(TC1H) }, + { "CPU 2 Package Alt. Temperature (TCBD)", SMC_KEY(TCBD) }, + { "CPU 2 Package Temperature (TC1D)", SMC_KEY(TC1D) }, + { "CPU 2 Proximity Raw Temperature (TC1p)", SMC_KEY(TC1p) }, + { "CPU Core 0 Absolute Raw Temperature PECI (TC0c)", SMC_KEY(TC0c) }, + { "CPU Core 1 Absolute Cooked Temperature PECI (TC1C)", SMC_KEY(TC1C) }, + { "CPU Core 1 Absolute Raw Temperature PECI (TC1c)", SMC_KEY(TC1c) }, + { "CPU Core 2 Absolute Cooked Temperature PECI (TC2C)", SMC_KEY(TC2C) }, + { "CPU Core 2 Absolute Raw Temperature PECI (TC2c)", SMC_KEY(TC2c) }, + { "CPU Core 3 Absolute Cooked Temperature PECI (TC3C)", SMC_KEY(TC3C) }, + { "CPU Core 3 Absolute Raw Temperature PECI (TC3c)", SMC_KEY(TC3c) }, + { "CPU Core 3 Temperature PECI (TC4C)", SMC_KEY(TC4C) }, + { "CPU Core 4 Absolute Raw Temperature PECI (TC4c)", SMC_KEY(TC4c) }, + { "CPU Core 5 Absolute Raw Temperature PECI (TC5c)", SMC_KEY(TC5c) }, + { "CPU Core 6 Absolute Raw Temperature PECI (TC6c)", SMC_KEY(TC6c) }, + { "CPU Core 7 Absolute Raw Temperature PECI (TC7c)", SMC_KEY(TC7c) }, + { "CPU Core 8 Absolute Raw Temperature PECI (TC8c)", SMC_KEY(TC8c) }, + { "CPU Core 9 Absolute Raw Temperature PECI (TC9c)", SMC_KEY(TC9c) }, + { "CPU Core PECI Temperature (TC0C)", SMC_KEY(TC0C) }, + { "CPU Die Raw Temperature (TC0d)", SMC_KEY(TC0d) }, + { "CPU Die Temperature (TC0D)", SMC_KEY(TC0D) }, + { "CPU eDRAM Hot Indicator PECI (TCMc)", SMC_KEY(TCMc) }, + { "CPU Gfx Core Absolute Cooked Temperature PECI (TCGC)", SMC_KEY(TCGC) }, + { "CPU Gfx Core Absolute Raw Temperature PECI (TCGc)", SMC_KEY(TCGc) }, + { "CPU Heatpipe Temperature (Th0H)", SMC_KEY(Th0H) }, + { "CPU Max Package Core Absolute Cooked Temperature PECI (TCXC)", SMC_KEY(TCXC) }, + { "CPU Max Package Core Absolute Raw Temperature PECI (TCXc)", SMC_KEY(TCXc) }, + { "CPU Max Package Core Relative Cooked Temperature PECI (TCXR)", SMC_KEY(TCXR) }, + { "CPU Max Package Core Relative Raw Temperature PECI (TCXr)", SMC_KEY(TCXr) }, + { "CPU PECI Die Filtered And Adjusted Temperature (TC0F)", SMC_KEY(TC0F) }, + { "CPU PECI Die Filtered Temperature (TC0E)", SMC_KEY(TC0E) }, + { "CPU PECI Die Temperature Adjustment (TC0G)", SMC_KEY(TC0G) }, + { "CPU PECI Die Temperature Filter Coeff (TCFC)", SMC_KEY(TCFC) }, + { "CPU PECI Die Temperature Max Error (TC0J)", SMC_KEY(TC0J) }, + { "CPU PECI Die Temperature Trend (TC0T)", SMC_KEY(TC0T) }, + { "CPU PECI Die Temperature Trend (TCTD)", SMC_KEY(TCTD) }, + { "CPU Proximity Raw Temperature (TC0p)", SMC_KEY(TC0p) }, + { "CPU Proximity Temperature (TC0P)", SMC_KEY(TC0P) }, + { "CPU Relative To ProcHot 1 (TCAC)", SMC_KEY(TCAC) }, + { "CPU Relative To ProcHot 2 (TCBC)", SMC_KEY(TCBC) }, + { "CPU System Agent Core Absolute Cooked Temperature PECI (TCSC)", SMC_KEY(TCSC) }, + { "CPU System Agent Core Absolute Raw Temperature PECI (TCSc)", SMC_KEY(TCSc) }, + { "CPU System Agent Core Temperature PECI (TCSA)", SMC_KEY(TCSA) }, + { "CPU VR Proximity Cooked Temperature (TC1P)", SMC_KEY(TC1P) }, + { "DCIn Air Flow Adjusted Temperature (TaSP)", SMC_KEY(TaSP) }, + { "DCIn Air Flow Temperature (Ta0P)", SMC_KEY(Ta0P) }, + { "DIMM 0 PECI Cooked Temperature (TM0D)", SMC_KEY(TM0D) }, + { "DIMM 0 Proximity Raw Temperature (TM0p)", SMC_KEY(TM0p) }, + { "DIMM 1 PECI Cooked Temperature (TM1D)", SMC_KEY(TM1D) }, + { "DIMM 1 Proximity Cooked Temperature (TM1P)", SMC_KEY(TM1P) }, + { "DIMM 1 Proximity Raw Temperature (TM1p)", SMC_KEY(TM1p) }, + { "DIMM 2 PECI Cooked Temperature (TM2D)", SMC_KEY(TM2D) }, + { "DIMM 2 Proximity Cooked Temperature (TM2P)", SMC_KEY(TM2P) }, + { "DIMM 2 Proximity Raw Temperature (TM2p)", SMC_KEY(TM2p) }, + { "DIMM 3 PECI Cooked Temperature (TM3D)", SMC_KEY(TM3D) }, + { "DIMM 3 Proximity Cooked Temperature (TM3P)", SMC_KEY(TM3P) }, + { "DIMM 3 Proximity Raw Temperature (TM3p)", SMC_KEY(TM3p) }, + { "DIMM Bandwidth Estimate (TMBS)", SMC_KEY(TMBS) }, + { "DIMM Max Cooked Temperature (TMXD)", SMC_KEY(TMXD) }, + { "DIMM Proximity Max Cooked Temperature (TMXP)", SMC_KEY(TMXP) }, + { "DIMM Virtual Temperature (TM0V)", SMC_KEY(TM0V) }, + { "DIMM Virtual Temperature For 2x DIMM Slot 1+2 Or 2+3 Config (TM2b)", SMC_KEY(TM2b) }, + { "DIMM Virtual Temperature For 2x DIMM Slot 1+2+3+4 Config (TM1a)", SMC_KEY(TM1a) }, + { "DIMM Virtual Temperature For 2x DIMM Slot 1+3 Config (TM2a)", SMC_KEY(TM2a) }, + { "DIMM Virtual Temperature For 2x DIMM Slot 1+4 Or 2+4 Config (TM2c)", SMC_KEY(TM2c) }, + { "DIMM Virtual Temperature For 2x DIMM Slot 3+4 Config (TM2d)", SMC_KEY(TM2d) }, + { "DIMM Virtual Temperature For 3x DIMM Slot 1+2+3 Config (TM3d)", SMC_KEY(TM3d) }, + { "DIMM Virtual Temperature For 3x DIMM Slot 1+2+4 Config (TM3c)", SMC_KEY(TM3c) }, + { "DIMM Virtual Temperature For 3x DIMM Slot 1+3+4 Config (TM3b)", SMC_KEY(TM3b) }, + { "DIMM Virtual Temperature For 3x DIMM Slot 2+3+4 Config (TM3a)", SMC_KEY(TM3a) }, + { "DIMM Virtual Temperature For 4x DIMM Slot 1+2+3+4 Config (TM4a)", SMC_KEY(TM4a) }, + { "Drive 0 Backup Virtual DRAM Temperature (TH0V)", SMC_KEY(TH0V) }, + { "Drive 0 OOBv1 Mapped Temperature (TH0O)", SMC_KEY(TH0O) }, + { "Drive 0 OOBv1 Raw Bit-Mapped Temperature (TH0o)", SMC_KEY(TH0o) }, + { "Drive 0 OOBv3 Absolute Cooked Temperature A (TH0A)", SMC_KEY(TH0A) }, + { "Drive 0 OOBv3 Absolute Cooked Temperature B (TH0B)", SMC_KEY(TH0B) }, + { "Drive 0 OOBv3 Absolute Cooked Temperature C (TH0C)", SMC_KEY(TH0C) }, + { "Drive 0 OOBv3 Absolute Raw Temperature A (TH0a)", SMC_KEY(TH0a) }, + { "Drive 0 OOBv3 Absolute Raw Temperature B (TH0b)", SMC_KEY(TH0b) }, + { "Drive 0 OOBv3 Absolute Raw Temperature C (TH0c)", SMC_KEY(TH0c) }, + { "Drive 0 OOBv3 Raw Temperature Max (TH0x)", SMC_KEY(TH0x) }, + { "Drive 0 OOBv3 Relative Cooked Temperature Max (TH0R)", SMC_KEY(TH0R) }, + { "Drive 0 OOBv3 Relative Filtered Temperature Max (TH0F)", SMC_KEY(TH0F) }, + { "Drive 0 Temperature Sensor Existence Used For TM0V (TH0e)", SMC_KEY(TH0e) }, + { "Drive 1 OOBv1 Filtered Temperature (TH1P)", SMC_KEY(TH1P) }, + { "Drive 1 OOBv1 Mapped Temperature (TH1O)", SMC_KEY(TH1O) }, + { "Drive 1 OOBv1 Raw Bit-Mapped Temperature (TH1o)", SMC_KEY(TH1o) }, + { "Drive 1 OOBv3 Absolute Cooked Temperature A (TH1A)", SMC_KEY(TH1A) }, + { "Drive 1 OOBv3 Absolute Cooked Temperature B (TH1B)", SMC_KEY(TH1B) }, + { "Drive 1 OOBv3 Absolute Cooked Temperature C (TH1C)", SMC_KEY(TH1C) }, + { "Drive 1 OOBv3 Absolute Raw Temperature A (TH1a)", SMC_KEY(TH1a) }, + { "Drive 1 OOBv3 Absolute Raw Temperature B (TH1b)", SMC_KEY(TH1b) }, + { "Drive 1 OOBv3 Absolute Raw Temperature C (TH1c)", SMC_KEY(TH1c) }, + { "Drive 1 OOBv3 Relative Cooked Temperature Max (TH1R)", SMC_KEY(TH1R) }, + { "Drive 1 OOBv3 Relative Filtered Temperature Max (TH1F)", SMC_KEY(TH1F) }, + { "EMC1428 Internal Diode Raw Temperature (Tm0p)", SMC_KEY(Tm0p) }, + { "Expansion Slots Temperature (TS0C)", SMC_KEY(TS0C) }, + { "Fan 0 Synthetic Temperature (TF0S)", SMC_KEY(TF0S) }, + { "Fan Target Temperature (TTF0)", SMC_KEY(TTF0) }, + { "Filtered Power Supply 1 Proximity Temperature (TpFP)", SMC_KEY(TpFP) }, + { "Filtered Vent Proximity Temperature (TVFP)", SMC_KEY(TVFP) }, + { "Fin Stack Temperature (THFH)", SMC_KEY(THFH) }, + { "GFX Memory Temperature (TG0M)", SMC_KEY(TG0M) }, + { "GPU 0 Die Cooked Temperature (TG0D)", SMC_KEY(TG0D) }, + { "GPU 0 Die Filtered And Adjusted Temperature (TG0F)", SMC_KEY(TG0F) }, + { "GPU 0 Die Filtered Temperature (TG0E)", SMC_KEY(TG0E) }, + { "GPU 0 Die Raw Temperature (TG0d)", SMC_KEY(TG0d) }, + { "GPU 0 Die Temperature Max Error (TG0J)", SMC_KEY(TG0J) }, + { "GPU 0 Die Temperature Trend (TG0T)", SMC_KEY(TG0T) }, + { "GPU 0 Proximity Cooked Temperature (TG0P)", SMC_KEY(TG0P) }, + { "GPU 0 Proximity Raw Temperature (TG0p)", SMC_KEY(TG0p) }, + { "GPU AMD Die Digital Temperature (TGDD)", SMC_KEY(TGDD) }, + { "GPU B VR Proximity Cooked Temperature (TG5P)", SMC_KEY(TG5P) }, + { "GPU B VRAM Proximity Cooked Temperature (TG4P)", SMC_KEY(TG4P) }, + { "GPU Die Analog Temperature (TGDF)", SMC_KEY(TGDF) }, + { "GPU Digital Die Filtered Temperature (TG1F)", SMC_KEY(TG1F) }, + { "GPU Digital Die Raw Temperature Without Offset (TG1d)", SMC_KEY(TG1d) }, + { "GPU Digital Die Temperature (TG1D)", SMC_KEY(TG1D) }, + { "GPU FB VR Proximity 3 Cooked Temperature (TG3P)", SMC_KEY(TG3P) }, + { "GPU FB VR Proximity 3 Raw Temperature (TG3p)", SMC_KEY(TG3p) }, + { "GPU GDDR5 Proximity 1 Cooked Temperature (TG1P)", SMC_KEY(TG1P) }, + { "GPU GDDR5 Proximity 1 Raw Temperature (TG1p)", SMC_KEY(TG1p) }, + { "GPU VR Proximity 2 Cooked Temperature (TG2P)", SMC_KEY(TG2P) }, + { "GPU VR Proximity 2 Raw Temperature (TG2p)", SMC_KEY(TG2p) }, + { "GPU VR Temperature (TGVP)", SMC_KEY(TGVP) }, + { "HDD Bay 3 Temperature (TH2P)", SMC_KEY(TH2P) }, + { "HDD Bay 4 Temperature (TH3P)", SMC_KEY(TH3P) }, + { "HDD Proximity Temperature (TH0P)", SMC_KEY(TH0P) }, + { "Heat Pipe Temperature (TG0H)", SMC_KEY(TG0H) }, + { "Heat Pipe Temperature 2 (TG1H)", SMC_KEY(TG1H) }, + { "Heat Spreader Proximity Temperature (Th0P)", SMC_KEY(Th0P) }, + { "High Speed I/O Proximity 0 Temperature (TI0P)", SMC_KEY(TI0P) }, + { "High Speed I/O Proximity 1 Temperature (TI1P)", SMC_KEY(TI1P) }, + { "LCD Filtered Center Front-Of-Screen Temperature Feeding TL1V (TL1v)", SMC_KEY(TL1v) }, + { "LCD Filtered Center Front-Of-Screen Temperature For Color Compensation (TL1V)", SMC_KEY(TL1V) }, + { "LCD Filtered Front-Of-Screen Hotspot Virtual Temperature (TL0V)", SMC_KEY(TL0V) }, + { "LCD IR Target Hotspot Calculated Temperature (TL2p)", SMC_KEY(TL2p) }, + { "LCD IR Temperature Sensor Die Raw Temperature (TL3p)", SMC_KEY(TL3p) }, + { "LCD TCON Proximity Cooked Temperature (TL1P)", SMC_KEY(TL1P) }, + { "LCD TCON Proximity Raw Temperature (TL1p)", SMC_KEY(TL1p) }, + { "LCD Unfiltered Front-Of-Screen Cooked Temperature (TL0P)", SMC_KEY(TL0P) }, + { "LCD Unfiltered Front-Of-Screen Raw Temperature (TL0p)", SMC_KEY(TL0p) }, + { "Left Fin Stack Temperature (Th2H)", SMC_KEY(Th2H) }, + { "Max PECI Reported Temperature (TCMX)", SMC_KEY(TCMX) }, + { "MCH Diode Temperature (TN0C)", SMC_KEY(TN0C) }, + { "MCH Heatsink Temperature (TN0H)", SMC_KEY(TN0H) }, + { "MCP Die 2 Temperature (TN1D)", SMC_KEY(TN1D) }, + { "MCP Die Temperature (TN0D)", SMC_KEY(TN0D) }, + { "MCP Proximity Temperature (TN0P)", SMC_KEY(TN0P) }, + { "Mem Bank B1 Temperature (TM8P)", SMC_KEY(TM8P) }, + { "Mem Bank B2 Temperature (TM9P)", SMC_KEY(TM9P) }, + { "Mem Module A2 Temperature (TM1S)", SMC_KEY(TM1S) }, + { "Mem Module A3 Temperature (TM2S)", SMC_KEY(TM2S) }, + { "Mem Module A4 Temperature (TM3S)", SMC_KEY(TM3S) }, + { "Mem Module B1 Temperature (TM8S)", SMC_KEY(TM8S) }, + { "Mem Module B2 Temperature (TM9S)", SMC_KEY(TM9S) }, + { "Memory Controller/Integrated Graphics PECI Temperature (TMCD)", SMC_KEY(TMCD) }, + { "Memory Proximity Temperature (TM0P)", SMC_KEY(TM0P) }, + { "MLB Bottom Side Temperature (Tm1P)", SMC_KEY(Tm1P) }, + { "MLB Proximity 0 Cooked Temperature (Tm0P)", SMC_KEY(Tm0P) }, + { "MLB Proximity 1 Raw Temperature (Tm1p)", SMC_KEY(Tm1p) }, + { "MLB Proximity 2 Cooked Temperature (Tm2P)", SMC_KEY(Tm2P) }, + { "MLB Proximity 2 Raw Temperature (Tm2p)", SMC_KEY(Tm2p) }, + { "MLB Proximity Temperature (TMLB)", SMC_KEY(TMLB) }, + { "MLB Temperature (Tp0P)", SMC_KEY(Tp0P) }, + { "NAND Temperature (Th0N)", SMC_KEY(Th0N) }, + { "Northbridge 2 Temperature (TN1P)", SMC_KEY(TN1P) }, + { "Optical Drive Temperature (TO0P)", SMC_KEY(TO0P) }, + { "Palm Rest Temperature (Ts0P)", SMC_KEY(Ts0P) }, + { "Palm Rest Temperature 2 (Ts1P)", SMC_KEY(Ts1P) }, + { "PCH Die Cooked Temperature (TPCD)", SMC_KEY(TPCD) }, + { "PCH Digital Die Raw Temperature (TPCd)", SMC_KEY(TPCd) }, + { "PCH Diode Temperature (TP0D)", SMC_KEY(TP0D) }, + { "PCH Proximity Temperature (TP0P)", SMC_KEY(TP0P) }, + { "PCI Slot 1 Pos 1 Temperature (TA0S)", SMC_KEY(TA0S) }, + { "PCI Slot 1 Pos 2 Temperature (TA1S)", SMC_KEY(TA1S) }, + { "PCI Slot 2 Pos 1 Temperature (TA2S)", SMC_KEY(TA2S) }, + { "PCI Slot 2 Pos 2 Temperature (TA3S)", SMC_KEY(TA3S) }, + { "Power Supply 1 Alt. Temperature (Tp0C)", SMC_KEY(Tp0C) }, + { "Power Supply 2 Alt. Temperature (Tp1C)", SMC_KEY(Tp1C) }, + { "Power Supply 3 Temperature (Tp2P)", SMC_KEY(Tp2P) }, + { "Power Supply 4 Temperature (Tp3P)", SMC_KEY(Tp3P) }, + { "Power Supply 5 Temperature (Tp4P)", SMC_KEY(Tp4P) }, + { "Power Supply 6 Temperature (Tp5P)", SMC_KEY(Tp5P) }, + { "Power Supply T2 Secondary Heatsink Cooked Temperature (Tp2H)", SMC_KEY(Tp2H) }, + { "Power Supply T2 Secondary Heatsink Filtered Temperature (Tp2F)", SMC_KEY(Tp2F) }, + { "Power Supply T2 Secondary Heatsink Raw Temperature (Tp2h)", SMC_KEY(Tp2h) }, + { "PSU Secondary Heatsink Diode Cooked Temperature (Tp0T)", SMC_KEY(Tp0T) }, + { "Right Fin Stack Temperature (Th1H)", SMC_KEY(Th1H) }, + { "RIO Temperature (Th0R)", SMC_KEY(Th0R) }, + { "S2 Camera Proximity Temperature (TS2P)", SMC_KEY(TS2P) }, + { "Secondary Power Supply Proximity Temperature (Tp1P)", SMC_KEY(Tp1P) }, + { "Skin 0 Raw Temperature (TS0p)", SMC_KEY(TS0p) }, + { "Skin 0 Virtual Temperature (TS0V)", SMC_KEY(TS0V) }, + { "Speaker Proximity 2 Temperature (TS1P)", SMC_KEY(TS1P) }, + { "Speaker Proximity Temperature (TS0P)", SMC_KEY(TS0P) }, + { "Speaker Remote 2 Temperature (TS1D)", SMC_KEY(TS1D) }, + { "Speaker Remote Temperature (TS0D)", SMC_KEY(TS0D) }, + { "SSD 0 OOBv3 Cooked Temperature Max (TH0X)", SMC_KEY(TH0X) }, + { "SSD 1 OOBv3 Cooked Temperature Max (TH1X)", SMC_KEY(TH1X) }, + { "Synthetic Bottom Skin Temperature (Ts0S)", SMC_KEY(Ts0S) }, + { "Synthetic DIMM Estimate (TM0S)", SMC_KEY(TM0S) }, + { "Synthetic Top Skin Temperature (Ts1S)", SMC_KEY(Ts1S) }, + { "TBT Proximity Raw Temperature (TI0p)", SMC_KEY(TI0p) }, + { "TBT Thermal Diode Raw Temperature (Te0t)", SMC_KEY(Te0t) }, + { "TBT Thermal Diode Temperature (Te0T)", SMC_KEY(Te0T) }, + { "Thermal Trap Hysteresis (TsTH)", SMC_KEY(TsTH) }, + { "Thermal Trap Threshold (TsTP)", SMC_KEY(TsTP) }, + { "Thermal Warning Hysteresis (TsHS)", SMC_KEY(TsHS) }, + { "Thermal Warning Threshold (TsWS)", SMC_KEY(TsWS) }, + { "Thunderbolt Die Temperature (THSP)", SMC_KEY(THSP) }, + { "Thunderbolt L Temperature (TTLD)", SMC_KEY(TTLD) }, + { "Thunderbolt Proximity Cooked Temperature (TI0T)", SMC_KEY(TI0T) }, + { "Thunderbolt R Temperature (TTRD)", SMC_KEY(TTRD) }, + { "Touchpad Temperature (Ts2S)", SMC_KEY(Ts2S) }, + { "Vent Proximity Temperature (TV0P)", SMC_KEY(TV0P) }, + { "WiFi Proximity Raw Temperature (TW0p)", SMC_KEY(TW0p) }, + { "Wireless Proximity Temperature (TW0P)", SMC_KEY(TW0P) }, +}; + +static const struct macsmc_sensor_desc power_sensors[] = { + { "12 V Rail (Pp0R)", SMC_KEY(Pp0R) }, + { "2nd GPU Plimit (MSTi)", SMC_KEY(MSTi) }, + { "3.3V In S0 Power (PR3C)", SMC_KEY(PR3C) }, + { "3.3V S0 Power (PR0C)", SMC_KEY(PR0C) }, + { "3.3V S3 Power (PR1C)", SMC_KEY(PR1C) }, + { "3.3V S5 Power (PR5C)", SMC_KEY(PR5C) }, + { "5V Lowside Power (P50R)", SMC_KEY(P50R) }, + { "A8 Load-Side Rail (PA8C)", SMC_KEY(PA8C) }, + { "Audio ScratchPad Register (MST1)", SMC_KEY(MST1) }, + { "Audio ScratchPad2 Register (MST2)", SMC_KEY(MST2) }, + { "Average Main Chipset Power (Pc0R)", SMC_KEY(Pc0R) }, + { "Battery Rail (PB0R)", SMC_KEY(PB0R) }, + { "Battery Rail (PBLC)", SMC_KEY(PBLC) }, + { "BL Rail 12 V (PBLR)", SMC_KEY(PBLR) }, + { "Chipset IMon Power (PCS1)", SMC_KEY(PCS1) }, + { "Chipset Lowside Power (PCS0)", SMC_KEY(PCS0) }, + { "CPU 1V5 Power (PD1R)", SMC_KEY(PD1R) }, + { "CPU Core (PCAC)", SMC_KEY(PCAC) }, + { "CPU Core 1 (PC0C)", SMC_KEY(PC0C) }, + { "CPU Core 2 (PC1C)", SMC_KEY(PC1C) }, + { "CPU Core 3 (PC2C)", SMC_KEY(PC2C) }, + { "CPU Core 4 (PC3C)", SMC_KEY(PC3C) }, + { "CPU Core 5 (PC4C)", SMC_KEY(PC4C) }, + { "CPU Core 6 (PC5C)", SMC_KEY(PC5C) }, + { "CPU Core 7 (PC6C)", SMC_KEY(PC6C) }, + { "CPU Core 8 (PC7C)", SMC_KEY(PC7C) }, + { "CPU Core IMON (PCAM)", SMC_KEY(PCAM) }, + { "CPU Cores (PCPC)", SMC_KEY(PCPC) }, + { "CPU DRAM (PCPD)", SMC_KEY(PCPD) }, + { "CPU GFX (PCPG)", SMC_KEY(PCPG) }, + { "CPU High-Side Average (PC0R)", SMC_KEY(PC0R) }, + { "CPU I/O High-Side (PC0I)", SMC_KEY(PC0I) }, + { "CPU I/O High-Side 2 (PC0M)", SMC_KEY(PC0M) }, + { "CPU I/O Load-Side Rail (PCIC)", SMC_KEY(PCIC) }, + { "CPU Integrated GPU (PC0G)", SMC_KEY(PC0G) }, + { "CPU Package Total PECI (PCPT)", SMC_KEY(PCPT) }, + { "CPU Package Total Power SMC (PCPR)", SMC_KEY(PCPR) }, + { "CPU Package Total Power SMC Load Sensors (PCLT)", SMC_KEY(PCLT) }, + { "CPU Plimit (MSTc)", SMC_KEY(MSTc) }, + { "CPU Rail (PC1R)", SMC_KEY(PC1R) }, + { "CPU Raw Package (PC0c)", SMC_KEY(PC0c) }, + { "CPU S0 Rail (PC5R)", SMC_KEY(PC5R) }, + { "CPU System Agent (PC0S)", SMC_KEY(PC0S) }, + { "CPU Total (PCPL)", SMC_KEY(PCPL) }, + { "CPU Total (PCTR)", SMC_KEY(PCTR) }, + { "CPU VccEDRAM (PCEC)", SMC_KEY(PCEC) }, + { "CPU VCCSA (PCSC)", SMC_KEY(PCSC) }, + { "CT Load-Side Rail (PCTC)", SMC_KEY(PCTC) }, + { "DC-In MLB S5 Rail (PD5R)", SMC_KEY(PD5R) }, + { "DC-In MLB Total (PDMR)", SMC_KEY(PDMR) }, + { "DDR (PM1C)", SMC_KEY(PM1C) }, + { "DDR Power 1.8V CPU (PM2C)", SMC_KEY(PM2C) }, + { "DDR S3 Power (PM3C)", SMC_KEY(PM3C) }, + { "DIMM Load-Side Power Per Fan RPM Squared (PM0f)", SMC_KEY(PM0f) }, + { "Discrete BMON On Battery Power (PB1R)", SMC_KEY(PB1R) }, + { "Drive 0 (PH0R)", SMC_KEY(PH0R) }, + { "Drive 0 Filtered Total Power (PH0F)", SMC_KEY(PH0F) }, + { "Drive 1 (PH1R)", SMC_KEY(PH1R) }, + { "Drive 1 Filtered Power (PH1F)", SMC_KEY(PH1F) }, + { "Drive 2 Power (PH2R)", SMC_KEY(PH2R) }, + { "External GPU 1.05 V (PG2C)", SMC_KEY(PG2C) }, + { "External GPU 1.35 V (PG3C)", SMC_KEY(PG3C) }, + { "External GPU 1.8 V (PG1C)", SMC_KEY(PG1C) }, + { "External GPU Rail 4 (PG4C)", SMC_KEY(PG4C) }, + { "F3 Load-Side Rail (PF3C)", SMC_KEY(PF3C) }, + { "Forced Idle Limit (MSTf)", SMC_KEY(MSTf) }, + { "GFX B Total Power (PG1R)", SMC_KEY(PG1R) }, + { "GPU (PG0C)", SMC_KEY(PG0C) }, + { "GPU 0 Rail (PG0R)", SMC_KEY(PG0R) }, + { "GPU A VDDCI Low Side Power (PG0S)", SMC_KEY(PG0S) }, + { "GPU Aux Input-Side Power (PG1A)", SMC_KEY(PG1A) }, + { "GPU Aux Load-Side Power (PG0A)", SMC_KEY(PG0A) }, + { "GPU B VDDCI Low Side Power (PG1S)", SMC_KEY(PG1S) }, + { "GPU Frame Buffer Input-Side Power (PG0F)", SMC_KEY(PG0F) }, + { "GPU Frame Buffer Input-Side Power (PG1F)", SMC_KEY(PG1F) }, + { "GPU Mem Ctl Load-Side Power (PG0M)", SMC_KEY(PG0M) }, + { "GPU Package Total Power SMC (PGPR)", SMC_KEY(PGPR) }, + { "GPU Plimit (MSTg)", SMC_KEY(MSTg) }, + { "GPU Total (PGTR)", SMC_KEY(PGTR) }, + { "GPU Uncore High-Side Power (PG0U)", SMC_KEY(PG0U) }, + { "GPU VDDCI Load-Side Power (PG0I)", SMC_KEY(PG0I) }, + { "GPU VRAM Load-Side Power (PG0V)", SMC_KEY(PG0V) }, + { "Heatpipe (PHPC)", SMC_KEY(PHPC) }, + { "HP Power Target (PTHC)", SMC_KEY(PTHC) }, + { "HP Power Throttle (MSLT)", SMC_KEY(MSLT) }, + { "I/O Board Total Power (PI0R)", SMC_KEY(PI0R) }, + { "Intel GPU IMON (PCGC)", SMC_KEY(PCGC) }, + { "Intel GPU IMON 2 (PCGM)", SMC_KEY(PCGM) }, + { "LCD Panel (PLDC)", SMC_KEY(PLDC) }, + { "Left Thunderbolt/I/O Rail (POLR)", SMC_KEY(POLR) }, + { "Left USB-C Load-Side Rail (PULC)", SMC_KEY(PULC) }, + { "Main 3.3 V Rail (PH02)", SMC_KEY(PH02) }, + { "Main 5 V Rail (PH05)", SMC_KEY(PH05) }, + { "MC Load-Side Rail (PMCC)", SMC_KEY(PMCC) }, + { "MCH (PN0C)", SMC_KEY(PN0C) }, + { "MCP Memory Power (PN1C)", SMC_KEY(PN1C) }, + { "MCP VCore Power (PN0R)", SMC_KEY(PN0R) }, + { "MEM Plimit (MSTm)", SMC_KEY(MSTm) }, + { "Memory Average (PM0C)", SMC_KEY(PM0C) }, + { "Memory Power (PZDM)", SMC_KEY(PZDM) }, + { "Memory Rail (PM0R)", SMC_KEY(PM0R) }, + { "Memory Total Power (PMTR)", SMC_KEY(PMTR) }, + { "Misc. Rail (PO0R)", SMC_KEY(PO0R) }, + { "ODD Power (PZOD)", SMC_KEY(PZOD) }, + { "Other 3.3V High Side Power (PO3R)", SMC_KEY(PO3R) }, + { "Other 5 V High-Side (PO5R)", SMC_KEY(PO5R) }, + { "PBus (PP0R)", SMC_KEY(PP0R) }, + { "PBus Battery Discharge (PPBR)", SMC_KEY(PPBR) }, + { "PCH Core Power (PSBC)", SMC_KEY(PSBC) }, + { "PCH Rail (PN1R)", SMC_KEY(PN1R) }, + { "Power Supply Filter Coefficient (PD0K)", SMC_KEY(PD0K) }, + { "Power Supply Filtered Power (PD0E)", SMC_KEY(PD0E) }, + { "Power Supply Max Error Filtered Output (PD0J)", SMC_KEY(PD0J) }, + { "Power Supply Power Filtered Then Adjusted (PD0F)", SMC_KEY(PD0F) }, + { "Power Supply Power Trend (PD0D)", SMC_KEY(PD0D) }, + { "Power Zone AP (PZAP)", SMC_KEY(PZAP) }, + { "Power Zone Backlight (PZBL)", SMC_KEY(PZBL) }, + { "Power Zone Storage (PZHD)", SMC_KEY(PZHD) }, + { "Right Thunderbolt/I/O Rail (PORR)", SMC_KEY(PORR) }, + { "Right USB-C Load-Side Rail (PURC)", SMC_KEY(PURC) }, + { "S0 5.0V Power (PR0R)", SMC_KEY(PR0R) }, + { "S1 Load-Side Rail (PS1C)", SMC_KEY(PS1C) }, + { "S2 Camera Power (PCMC)", SMC_KEY(PCMC) }, + { "S2 Camera Power (PS2C)", SMC_KEY(PS2C) }, + { "S3 3.30V Power (PR1R)", SMC_KEY(PR1R) }, + { "S3 5.0V Power (PR2R)", SMC_KEY(PR2R) }, + { "S5 3.30V Power (PR3R)", SMC_KEY(PR3R) }, + { "SL Rail 3.3 V (PSLC)", SMC_KEY(PSLC) }, + { "SSD 3.3 V Load-Side Rail 0 (PH0C)", SMC_KEY(PH0C) }, + { "SSD 3.3 V Load-Side Rail 1 (PH1C)", SMC_KEY(PH1C) }, + { "SSD Power (PHDC)", SMC_KEY(PHDC) }, + { "SSD Power (PSDC)", SMC_KEY(PSDC) }, + { "System Total, 1 s Delayed (PSTR)", SMC_KEY(PSTR) }, + { "T101 Accuator Power (PTPC)", SMC_KEY(PTPC) }, + { "T25 Track Pad Power (PTPR)", SMC_KEY(PTPR) }, + { "Thunderbolt Power (PHSC)", SMC_KEY(PHSC) }, + { "Thunderbolt Power (PHSP)", SMC_KEY(PHSP) }, + { "WiFi (PAPC)", SMC_KEY(PAPC) }, + { "Wifi Load-Side Power (PW0R)", SMC_KEY(PW0R) }, + { "Heatpipe Average (PZ0G)", SMC_KEY(PZ0G) }, + { "Heatpipe Average Target (PZ0E)", SMC_KEY(PZ0E) }, + { "Heatpipe Filtered (PZ0F)", SMC_KEY(PZ0F) }, + { "Heatpipe Throttle (PZ0T)", SMC_KEY(PZ0T) }, + { "CPU Average (PZ1G)", SMC_KEY(PZ1G) }, + { "CPU Filtered (PZ1F)", SMC_KEY(PZ1F) }, + { "CPU Target (PZ1E)", SMC_KEY(PZ1E) }, + { "CPU Throttle (PZ1T)", SMC_KEY(PZ1T) }, + { "dGPU Average (PZ2G)", SMC_KEY(PZ2G) }, + { "dGPU Filtered (PZ2F)", SMC_KEY(PZ2F) }, + { "dGPU Target (PZ2E)", SMC_KEY(PZ2E) }, + { "dGPU Throttle (PZ2T)", SMC_KEY(PZ2T) }, + { "Batt aux Average (PZ3G)", SMC_KEY(PZ3G) }, + { "Batt aux Filtered (PZ3F)", SMC_KEY(PZ3F) }, + { "Batt aux Target (PZ3E)", SMC_KEY(PZ3E) }, + { "Batt aux Throttle (PZ3T)", SMC_KEY(PZ3T) }, + { "Battery Average (PZ4G)", SMC_KEY(PZ4G) }, + { "Battery Filtered (PZ4F)", SMC_KEY(PZ4F) }, + { "Battery Target (PZ4E)", SMC_KEY(PZ4E) }, + { "Battery Throttle (PZ4T)", SMC_KEY(PZ4T) }, + { "Zone 5 Abstract Throttle (PZ5T)", SMC_KEY(PZ5T) }, + { "Zone 5 Average Power (PZ5G)", SMC_KEY(PZ5G) }, + { "Zone 5 Filtered Power (PZ5F)", SMC_KEY(PZ5F) }, + { "Zone 5 Target Power (PZ5E)", SMC_KEY(PZ5E) }, +}; + +static const struct macsmc_sensor_desc current_sensors[] = { + { "3.3V S0 Current (IR0C)", SMC_KEY(IR0C) }, + { "3.3V S0 Current (IR3C)", SMC_KEY(IR3C) }, + { "5.0V S0 Current (IR5C)", SMC_KEY(IR5C) }, + { "5V Lowside Current (I50R)", SMC_KEY(I50R) }, + { "Airport Current (IZOP)", SMC_KEY(IZOP) }, + { "Backlight Current (IBLC)", SMC_KEY(IBLC) }, + { "Battery Current (IBAC)", SMC_KEY(IBAC) }, + { "Battery Current Discrete (IP0R)", SMC_KEY(IP0R) }, + { "Battery Discharge Current MLB (IB0R)", SMC_KEY(IB0R) }, + { "Camera S2 Current (ICMC)", SMC_KEY(ICMC) }, + { "CPU 1V5 Current (ID1R)", SMC_KEY(ID1R) }, + { "CPU And MEM Current (IM0C)", SMC_KEY(IM0C) }, + { "CPU AXG Low-Side Current (IC0G)", SMC_KEY(IC0G) }, + { "CPU Core Current (IC0C)", SMC_KEY(IC0C) }, + { "CPU Core Current (ICS0)", SMC_KEY(ICS0) }, + { "CPU Current From CPU IMON (ICS1)", SMC_KEY(ICS1) }, + { "CPU DDR Current (IC3C)", SMC_KEY(IC3C) }, + { "CPU DDR Current (IM1C)", SMC_KEY(IM1C) }, + { "CPU High Side Current (IC0R)", SMC_KEY(IC0R) }, + { "CPU High Side Current From EMC1704 (IC1R)", SMC_KEY(IC1R) }, + { "CPU I/O High-Side Current (IC0I)", SMC_KEY(IC0I) }, + { "CPU Mem Low-Side Current (IC0M)", SMC_KEY(IC0M) }, + { "CPU Riser 12V High Side Current (ICTR)", SMC_KEY(ICTR) }, + { "CPU VCCIO Current (IC1C)", SMC_KEY(IC1C) }, + { "CPU VCCSA Current (IC2C)", SMC_KEY(IC2C) }, + { "CPU VSA Low Side Current (IC0S)", SMC_KEY(IC0S) }, + { "CSreg Current (Ic0R)", SMC_KEY(Ic0R) }, + { "DDR S3 Current (IM3C)", SMC_KEY(IM3C) }, + { "DIMM Current (IZDM)", SMC_KEY(IZDM) }, + { "DIMM Load-Side Current (IM0R)", SMC_KEY(IM0R) }, + { "Discrete Battery Current (IPB1)", SMC_KEY(IPB1) }, + { "Drive 0 12V Load-Side Current (IH02)", SMC_KEY(IH02) }, + { "Drive 0 5V Load-Side Current (IH05)", SMC_KEY(IH05) }, + { "Drive 1 3.3V Load-Side Current (IH1R)", SMC_KEY(IH1R) }, + { "Ext GPU 1.05V Current (IG2C)", SMC_KEY(IG2C) }, + { "Ext GPU 1.35V Current (IG3C)", SMC_KEY(IG3C) }, + { "Ext GPU High Side Current (IG0R)", SMC_KEY(IG0R) }, + { "GFX B Riser 12V High Side Current (IG1R)", SMC_KEY(IG1R) }, + { "GFX Vcore Current (IN0R)", SMC_KEY(IN0R) }, + { "GPU A VDDCI Low Side Current (IG0S)", SMC_KEY(IG0S) }, + { "GPU Aux Input-Side Current (IG1A)", SMC_KEY(IG1A) }, + { "GPU B VDDCI Low Side Current (IG1S)", SMC_KEY(IG1S) }, + { "GPU Core Current (IG0C)", SMC_KEY(IG0C) }, + { "GPU Core Input-Side Current (IG1C)", SMC_KEY(IG1C) }, + { "GPU FB High-Side Current (IG0F)", SMC_KEY(IG0F) }, + { "GPU FB Input-Side Current (IG1F)", SMC_KEY(IG1F) }, + { "GPU Uncore High-Side Current (IG0U)", SMC_KEY(IG0U) }, + { "GPU VDDCI Load-Side Current (IG0I)", SMC_KEY(IG0I) }, + { "HDD Current (IZHD)", SMC_KEY(IZHD) }, + { "I/O Board 12V High Side Current (II0R)", SMC_KEY(II0R) }, + { "Internal GFX Core Current (IN0C)", SMC_KEY(IN0C) }, + { "LCD Backlight Current (IZBL)", SMC_KEY(IZBL) }, + { "LCD Panel Current (ILDC)", SMC_KEY(ILDC) }, + { "LPDDR Current 1.8V (IM2C)", SMC_KEY(IM2C) }, + { "MCP DDR Current (IN1C)", SMC_KEY(IN1C) }, + { "Memory 1V5 High Side Current (IMTR)", SMC_KEY(IMTR) }, + { "ODD Current (IODC)", SMC_KEY(IODC) }, + { "ODD Current (IZOD)", SMC_KEY(IZOD) }, + { "Other 3.3V High Side Current (IO3R)", SMC_KEY(IO3R) }, + { "Other 5V High Side Current (IO5R)", SMC_KEY(IO5R) }, + { "Other High Side Current (IO0R)", SMC_KEY(IO0R) }, + { "Other High Side Current (IR1C)", SMC_KEY(IR1C) }, + { "PBus On Battery Current (IPBR)", SMC_KEY(IPBR) }, + { "PCH 1V05 Current (IN1R)", SMC_KEY(IN1R) }, + { "PCH Core Current (ISBC)", SMC_KEY(ISBC) }, + { "PCH/GPU/TBT 1.05V High-Side Current (IR1R)", SMC_KEY(IR1R) }, + { "Power Supply 12V Current Dynamic Filter Coeff (ID2L)", SMC_KEY(ID2L) }, + { "Power Supply 12V Current Filter Input (ID2I)", SMC_KEY(ID2I) }, + { "Power Supply 12V Current Filtered (ID2E)", SMC_KEY(ID2E) }, + { "Power Supply 12V Current Filtered And Adjusted (ID2F)", SMC_KEY(ID2F) }, + { "Power Supply 12V Current Max Error (ID2J)", SMC_KEY(ID2J) }, + { "Power Supply 12V Current Trend (ID2T)", SMC_KEY(ID2T) }, + { "S2 Camera Current (IS2C)", SMC_KEY(IS2C) }, + { "S3 5.0V Current (IR2C)", SMC_KEY(IR2C) }, + { "SSD 3V3 Low Side Current (IH0R)", SMC_KEY(IH0R) }, + { "SSD Current (IHDC)", SMC_KEY(IHDC) }, + { "SSD Current (ISDC)", SMC_KEY(ISDC) }, + { "Thunderbolt Current (IHSC)", SMC_KEY(IHSC) }, + { "Thunderbolt Current (IHSP)", SMC_KEY(IHSP) }, + { "Trackpad Actuator Current (ITPC)", SMC_KEY(ITPC) }, + { "Wifi Load-Side Current (IW0R)", SMC_KEY(IW0R) }, + { "WLAN Current (IZAP)", SMC_KEY(IZAP) }, + { "WLAN Lowside Current (IAPC)", SMC_KEY(IAPC) }, +}; + +static const struct macsmc_sensor_desc voltage_sensors[] = { + { "1.05V To CPU/PCH Lowside Voltage (VC1C)", SMC_KEY(VC1C) }, + { "1.2V To CPU/MEM Lowside Voltage (VM0C)", SMC_KEY(VM0C) }, + { "1.8V S3 Lowside Voltage (VM1C)", SMC_KEY(VM1C) }, + { "3.3V Load-Side Voltage (VR3R)", SMC_KEY(VR3R) }, + { "5V Lowside Voltage (V50R)", SMC_KEY(V50R) }, + { "ACC Voltage (VACC)", SMC_KEY(VACC) }, + { "ACDC Cooked Voltage (Vp0C)", SMC_KEY(Vp0C) }, + { "Backlight Output Voltage (VBLC)", SMC_KEY(VBLC) }, + { "Backlight Voltage (VZBL)", SMC_KEY(VZBL) }, + { "CPU AXG Low-Side Voltage (VC0G)", SMC_KEY(VC0G) }, + { "CPU Core Voltage (VC0C)", SMC_KEY(VC0C) }, + { "CPU Core Voltage (VCS0)", SMC_KEY(VCS0) }, + { "CPU High Side Voltage From EMC1704 (VC1R)", SMC_KEY(VC1R) }, + { "CPU Mem Load-Side Voltage (VC0M)", SMC_KEY(VC0M) }, + { "CPU Ripple Voltage (VCRC)", SMC_KEY(VCRC) }, + { "CPU Ripple Voltage (VCRP)", SMC_KEY(VCRP) }, + { "CPU VCCSA Voltage (VC2C)", SMC_KEY(VC2C) }, + { "CPU VSA Low Side Voltage (VC0S)", SMC_KEY(VC0S) }, + { "DIMM Load-Side Voltage (VM0R)", SMC_KEY(VM0R) }, + { "Drive 0 5V Load-Side Voltage (VH05)", SMC_KEY(VH05) }, + { "FIVR CPU Supply Voltage (VCFR)", SMC_KEY(VCFR) }, + { "GFX Vcore Voltage (VN0R)", SMC_KEY(VN0R) }, + { "GPU A VDDCI Low Side Voltage (VG0S)", SMC_KEY(VG0S) }, + { "GPU B VDDCI Low Side Voltage (VG1S)", SMC_KEY(VG1S) }, + { "GPU Core Input-Side Voltage (VG1C)", SMC_KEY(VG1C) }, + { "GPU Core Voltage (VG0C)", SMC_KEY(VG0C) }, + { "GPU Frame Buffer Input-Side Voltage (VG0F)", SMC_KEY(VG0F) }, + { "GPU Frame Buffer Input-Side Voltage (VG1F)", SMC_KEY(VG1F) }, + { "GPU Uncore High-Side Voltage (VG0U)", SMC_KEY(VG0U) }, + { "GPU VDDCI Load-Side Voltage (VG0I)", SMC_KEY(VG0I) }, + { "LCD IR Temp Sensor Voltage Raw Register (VL3t)", SMC_KEY(VL3t) }, + { "MCP Core Voltage (VN0C)", SMC_KEY(VN0C) }, + { "MCP Memory Voltage (VN1C)", SMC_KEY(VN1C) }, + { "Memory Voltage (VZDM)", SMC_KEY(VZDM) }, + { "ODD Voltage (VODC)", SMC_KEY(VODC) }, + { "ODD Voltage (VZOD)", SMC_KEY(VZOD) }, + { "PBus Rail Voltage (VP0R)", SMC_KEY(VP0R) }, + { "PCH Low-Side Voltage (VN1R)", SMC_KEY(VN1R) }, + { "PCH/GPU/TBT Load-Side Voltage (VR1R)", SMC_KEY(VR1R) }, + { "PSU Cooked Temperature As Voltage (VP0T)", SMC_KEY(VP0T) }, + { "SD Card Voltage (VSDC)", SMC_KEY(VSDC) }, + { "SSD 3.3V Low-Side Voltage (VH1R)", SMC_KEY(VH1R) }, + { "SSD 3V3 Low Side Voltage (VH0R)", SMC_KEY(VH0R) }, + { "SSD Voltage (VZHD)", SMC_KEY(VZHD) }, + { "T101 Accuator Voltage (VTPC)", SMC_KEY(VTPC) }, + { "WIFI Voltage (VZAP)", SMC_KEY(VZAP) }, + { "Wireless Voltage (VAPC)", SMC_KEY(VAPC) }, +}; + +static int macsmc_hwmon_create_sensor_acpi(struct apple_smc *smc, + struct macsmc_hwmon_sensor *sensor, smc_key key, char *name, u32 attrs) +{ + int ret; + + ret = apple_smc_get_key_info(smc, key, &sensor->info); + if (ret) + return ret; + + sensor->macsmc_key = key; + sensor->label = name; + sensor->attrs = attrs; + + return 0; +} /* * Fan data is exposed by the SMC as multiple sensors. * @@ -871,6 +1475,57 @@ static int macsmc_hwmon_create_fan(struct device *dev, struct apple_smc *smc, return 0; } +static int macsmc_hwmon_create_fan_acpi(struct apple_smc *smc, + struct macsmc_hwmon_fan *fan, int num) +{ + const char num_char = num + '0'; + int ret; + + ret = macsmc_hwmon_create_sensor_acpi(smc, &fan->now, + __SMC_KEY('F', num_char, 'A', 'c'), NULL, 0); + if (ret) + return ret; + + if (apple_smc_key_exists(smc, __SMC_KEY('F', num_char, 'I', 'D'))) { + char buf[17]; + + ret = apple_smc_read(smc, __SMC_KEY('F', num_char, 'I', 'D'), buf, 16); + if (ret) + return ret; + + buf[16] = '\0'; + snprintf(fan->label, sizeof(fan->label), "%s", buf + 4); + } else + snprintf(fan->label, sizeof(fan->label), "Fan %d", num); + + ret = macsmc_hwmon_create_sensor_acpi(smc, &fan->min, + __SMC_KEY('F', num_char, 'M', 'n'), NULL, 0); + if (ret) + return ret; + + ret = macsmc_hwmon_create_sensor_acpi(smc, &fan->max, + __SMC_KEY('F', num_char, 'M', 'x'), NULL, 0); + if (ret) + return ret; + + ret = macsmc_hwmon_create_sensor_acpi(smc, &fan->set, + __SMC_KEY('F', num_char, 'T', 'g'), NULL, 0); + if (ret) + return ret; + + if (apple_smc_key_exists(smc, __SMC_KEY('F', num_char, 'M', 'd'))) { + ret = macsmc_hwmon_create_sensor_acpi(smc, &fan->mode, + __SMC_KEY('F', num_char, 'M', 'd'), NULL, 0); + if (ret) + return ret; + } + + fan->attrs = HWMON_F_INPUT | HWMON_F_LABEL | HWMON_F_MIN | HWMON_F_MAX | HWMON_F_TARGET; + fan->manual = false; + + return 0; +} + static int macsmc_hwmon_populate_sensors(struct macsmc_hwmon *hwmon, struct device_node *hwmon_node) { @@ -907,7 +1562,7 @@ static int macsmc_hwmon_populate_sensors(struct macsmc_hwmon *hwmon, if (n_fan) { hwmon->fan.fans = devm_kcalloc(hwmon->dev, n_fan, - sizeof(struct macsmc_hwmon_fan), GFP_KERNEL); + sizeof(struct macsmc_hwmon_fan), GFP_KERNEL); if (!hwmon->fan.fans) return -ENOMEM; @@ -990,6 +1645,101 @@ static int macsmc_hwmon_populate_sensors(struct macsmc_hwmon *hwmon, return 0; } +static int macsmc_hwmon_register_sensors_acpi( + struct macsmc_hwmon *hwmon, + struct macsmc_hwmon_sensors *sensors, + const struct macsmc_sensor_desc *descs, + size_t num_descs, + u32 attrs) +{ + size_t count = 0; + size_t i; + int ret; + + for (i = 0; i < num_descs; i++) { + if (apple_smc_key_exists(hwmon->smc, descs[i].key)) + count++; + } + + if (!count) + return 0; + + sensors->sensors = devm_kcalloc(hwmon->dev, count, + sizeof(*sensors->sensors), + GFP_KERNEL); + if (!sensors->sensors) + return -ENOMEM; + + sensors->count = 0; + + for (i = 0; i < num_descs; i++) { + if (!apple_smc_key_exists(hwmon->smc, descs[i].key)) + continue; + + ret = macsmc_hwmon_create_sensor_acpi(hwmon->smc, + &sensors->sensors[sensors->count], + descs[i].key, + descs[i].name, + attrs); + if (ret) + return ret; + + sensors->count++; + } + + return 0; +} + +static int macsmc_hwmon_populate_sensors_acpi(struct macsmc_hwmon *hwmon) +{ + int ret, i; + + ret = apple_smc_read_u8(hwmon->smc, SMC_KEY(FNum), &hwmon->fan.count); + if (hwmon->fan.count && !ret) { + hwmon->fan.fans = devm_kcalloc(hwmon->dev, hwmon->fan.count, + sizeof(struct macsmc_hwmon_fan), GFP_KERNEL); + if (!hwmon->fan.fans) + return -ENOMEM; + + hwmon->fan.has_old_manual = apple_smc_key_exists(hwmon->smc, + __SMC_KEY('F', 'S', '!', ' ')); + + for (i = 0; i < hwmon->fan.count; i++) { + macsmc_hwmon_create_fan_acpi(hwmon->smc, &hwmon->fan.fans[i], i); + if (ret) + return ret; + } + } + ret = macsmc_hwmon_register_sensors_acpi(hwmon, &hwmon->temp, + temp_sensors, + ARRAY_SIZE(temp_sensors), + HWMON_T_INPUT | HWMON_T_LABEL); + if (ret) + return ret; + + ret = macsmc_hwmon_register_sensors_acpi(hwmon, &hwmon->power, + power_sensors, + ARRAY_SIZE(power_sensors), + HWMON_P_INPUT | HWMON_P_LABEL); + if (ret) + return ret; + + ret = macsmc_hwmon_register_sensors_acpi(hwmon, &hwmon->curr, + current_sensors, + ARRAY_SIZE(current_sensors), + HWMON_C_INPUT | HWMON_C_LABEL); + if (ret) + return ret; + + ret = macsmc_hwmon_register_sensors_acpi(hwmon, &hwmon->volt, + voltage_sensors, + ARRAY_SIZE(voltage_sensors), + HWMON_I_INPUT | HWMON_I_LABEL); + if (ret) + return ret; + + return 0; +} /* Create NULL-terminated config arrays */ static void macsmc_hwmon_populate_configs(u32 *configs, const struct macsmc_hwmon_sensors *sensors) { @@ -1090,9 +1840,9 @@ static int macsmc_hwmon_probe(struct platform_device *pdev) /* * The MFD driver will try to probe us unconditionally. Some devices * with the SMC do not have hwmon capabilities. Only probe if we have - * a hwmon node. + * a hwmon node or the machine is a intel mac. */ - if (!pdev->dev.of_node) + if (!pdev->dev.of_node && !smc->is_acpi) return -ENODEV; hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), @@ -1102,8 +1852,12 @@ static int macsmc_hwmon_probe(struct platform_device *pdev) hwmon->dev = &pdev->dev; hwmon->smc = smc; + platform_set_drvdata(pdev, hwmon); - ret = macsmc_hwmon_populate_sensors(hwmon, hwmon->dev->of_node); + if (hwmon->smc->is_acpi) + ret = macsmc_hwmon_populate_sensors_acpi(hwmon); + else + ret = macsmc_hwmon_populate_sensors(hwmon, hwmon->dev->of_node); if (ret) { dev_err(hwmon->dev, "Could not parse sensors\n"); return ret; @@ -1142,6 +1896,30 @@ static int macsmc_hwmon_probe(struct platform_device *pdev) return 0; } +static int macsmc_hwmon_resume(struct platform_device *pdev) +{ + struct macsmc_hwmon *hwmon = dev_get_drvdata(&pdev->dev); + + if (hwmon->smc->is_acpi && !hwmon->fan.has_old_manual) { + int idx; + int ret; + + for (idx = 0; idx < hwmon->fan.count; idx++) + if (hwmon->fan.fans[idx].manual) { + ret = macsmc_hwmon_write_key(hwmon->smc, + &hwmon->fan.fans[idx].mode, 1); + if (ret < 0) { + dev_warn(&pdev->dev, + "Unable to reenable fan manual, disabling\n"); + hwmon->fan.fans[idx].manual = false; + } + } + + } + + return 0; +} + static const struct of_device_id macsmc_hwmon_of_table[] = { { .compatible = "apple,smc-hwmon" }, {} @@ -1150,6 +1928,7 @@ MODULE_DEVICE_TABLE(of, macsmc_hwmon_of_table); static struct platform_driver macsmc_hwmon_driver = { .probe = macsmc_hwmon_probe, + .resume = macsmc_hwmon_resume, .driver = { .name = "macsmc-hwmon", .of_match_table = macsmc_hwmon_of_table, @@ -1160,3 +1939,4 @@ module_platform_driver(macsmc_hwmon_driver); MODULE_DESCRIPTION("Apple Silicon SMC hwmon driver"); MODULE_AUTHOR("James Calligeros "); MODULE_LICENSE("Dual MIT/GPL"); +MODULE_ALIAS("platform:macsmc-hwmon"); -- 2.55.0