* [PATCH v3 0/5] ARM: r9a06g032: add support for the watchdogs
@ 2022-02-21 9:50 Jean-Jacques Hiblot
2022-02-21 9:50 ` [PATCH v3 2/5] dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1 Jean-Jacques Hiblot
2022-02-21 9:50 ` [PATCH v3 5/5] watchdog: Add Renesas RZ/N1 Watchdog driver Jean-Jacques Hiblot
0 siblings, 2 replies; 4+ messages in thread
From: Jean-Jacques Hiblot @ 2022-02-21 9:50 UTC (permalink / raw)
To: linux-renesas-soc, geert+renesas, Wim Van Sebroeck, Guenter Roeck,
Magnus Damm, Rob Herring, Wolfram Sang
Cc: Jean-Jacques Hiblot, linux-watchdog, devicetree, linux-kernel
Hi all,
This series adds support for the watchdog timers of the RZ/N1.
The watchdog driver (rzn1-wdt.c) is derived from the driver available at
https://github.com/renesas-rz/rzn1_linux.git with a few modifications
In order to be able to reset the board when a watchdog timer expires,
the RSTEN register must be configured. it is the responsability of the
bootloader to set those bits (or not, depending on the chosen policy).
If the watchdog reset source is not enabled, an interrupt is triggered
when the watchdog expires. Currently this interrupt doesn't much apart
from printing a message.
Changes v2 -> v3:
* dts: changed compatible strings to include "renesas,r9a06g032-wdt" and
"renesas,rzn1-wdt".
* driver: removed the SOC-specific "renesas,r9a06g032-wdt".
* removed all the changes in the clock driver: the watchdog reset source
are not disabled anymore when the machine is halted.
* fixed the clock rate type in the computations.
* removed unnecessary printout and call to clk_disable_unprepare() in the
driver probe().
Changes v1 -> v2:
* Modified the clock driver to not enable the watchdog reset sources.
On other renesas platforms, those bits are by the bootloader. The
watchdog reset sources are still disabled when the platform is halted
to prevent a watchdog reset.
* Added a SOC-specific compatible "renesas,r9a06g032-wdt"
* reordered the dts/i entries
* default timeout is 60 seconds
* reworked the probe function of the wdt driver to better error cases
* removed the set_timeout() and use a fixed period computed in probe().
This removes the confusion and makes it clear that the period defined
by the user space in indeed handled by the watchdog core
Jean-Jacques Hiblot (4):
dt-bindings: clock: r9a06g032: Add the definition of the watchdog
clock
dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1
ARM: dts: r9a06g032: Add the watchdog nodes
ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeout
Phil Edworthy (1):
watchdog: Add Renesas RZ/N1 Watchdog driver
.../bindings/watchdog/renesas,wdt.yaml | 6 +
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 5 +
arch/arm/boot/dts/r9a06g032.dtsi | 16 ++
drivers/watchdog/Kconfig | 8 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/rzn1_wdt.c | 206 ++++++++++++++++++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 1 +
7 files changed, 243 insertions(+)
create mode 100644 drivers/watchdog/rzn1_wdt.c
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v3 2/5] dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1 2022-02-21 9:50 [PATCH v3 0/5] ARM: r9a06g032: add support for the watchdogs Jean-Jacques Hiblot @ 2022-02-21 9:50 ` Jean-Jacques Hiblot 2022-02-21 9:50 ` [PATCH v3 5/5] watchdog: Add Renesas RZ/N1 Watchdog driver Jean-Jacques Hiblot 1 sibling, 0 replies; 4+ messages in thread From: Jean-Jacques Hiblot @ 2022-02-21 9:50 UTC (permalink / raw) To: linux-renesas-soc, geert+renesas, Wim Van Sebroeck, Guenter Roeck, Wolfram Sang Cc: Jean-Jacques Hiblot, Rob Herring, Rob Herring, linux-watchdog, devicetree, linux-kernel Describe the WDT hardware in the RZ/N1 series. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 91a98ccd4226..b453af2dee3b 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -19,6 +19,11 @@ properties: - renesas,r7s9210-wdt # RZ/A2 - const: renesas,rza-wdt # RZ/A + - items: + - enum: + - renesas,r9a06g032-wdt # RZ/N1D + - const: renesas,rzn1-wdt # RZ/N1 + - items: - enum: - renesas,r9a07g044-wdt # RZ/G2{L,LC} @@ -89,6 +94,7 @@ allOf: contains: enum: - renesas,rza-wdt + - renesas,rzn1-wdt then: required: - power-domains -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 5/5] watchdog: Add Renesas RZ/N1 Watchdog driver 2022-02-21 9:50 [PATCH v3 0/5] ARM: r9a06g032: add support for the watchdogs Jean-Jacques Hiblot 2022-02-21 9:50 ` [PATCH v3 2/5] dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1 Jean-Jacques Hiblot @ 2022-02-21 9:50 ` Jean-Jacques Hiblot 2022-03-09 8:23 ` Jean-Jacques Hiblot 1 sibling, 1 reply; 4+ messages in thread From: Jean-Jacques Hiblot @ 2022-02-21 9:50 UTC (permalink / raw) To: linux-renesas-soc, geert+renesas, Wim Van Sebroeck, Guenter Roeck Cc: Phil Edworthy, Jean-Jacques Hiblot, linux-kernel, linux-watchdog From: Phil Edworthy <phil.edworthy@renesas.com> This is a driver for the standard WDT on the RZ/N1 devices. This WDT has very limited timeout capabilities. However, it can reset the device. To do so, the corresponding bits in the SysCtrl RSTEN register need to be enabled. This is not done by this driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> --- drivers/watchdog/Kconfig | 8 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/rzn1_wdt.c | 206 ++++++++++++++++++++++++++++++++++++ 3 files changed, 215 insertions(+) create mode 100644 drivers/watchdog/rzn1_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index c8fa79da23b3..ba6e4ebef404 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -883,6 +883,14 @@ config RENESAS_RZAWDT This driver adds watchdog support for the integrated watchdogs in the Renesas RZ/A SoCs. These watchdogs can be used to reset a system. +config RENESAS_RZN1WDT + tristate "Renesas RZ/N1 watchdog" + depends on ARCH_RENESAS || COMPILE_TEST + select WATCHDOG_CORE + help + This driver adds watchdog support for the integrated watchdogs in the + Renesas RZ/N1 SoCs. These watchdogs can be used to reset a system. + config RENESAS_RZG2LWDT tristate "Renesas RZ/G2L WDT Watchdog" depends on ARCH_RENESAS || COMPILE_TEST diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index f7da867e8782..38d38564f47b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o +obj-$(CONFIG_RENESAS_RZN1WDT) += rzn1_wdt.o obj-$(CONFIG_RENESAS_RZG2LWDT) += rzg2l_wdt.o obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o diff --git a/drivers/watchdog/rzn1_wdt.c b/drivers/watchdog/rzn1_wdt.c new file mode 100644 index 000000000000..7f5884e5d460 --- /dev/null +++ b/drivers/watchdog/rzn1_wdt.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/N1 Watchdog timer. + * This is a 12-bit timer driver from a (62.5/16384) MHz clock. It can't even + * cope with 2 seconds. + * + * Copyright 2018 Renesas Electronics Europe Ltd. + * + * Derived from Ralink RT288x watchdog timer. + */ + +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/watchdog.h> + +#define DEFAULT_TIMEOUT 60 + +#define RZN1_WDT_RETRIGGER 0x0 +#define RZN1_WDT_RETRIGGER_RELOAD_VAL 0 +#define RZN1_WDT_RETRIGGER_RELOAD_VAL_MASK 0xfff +#define RZN1_WDT_RETRIGGER_PRESCALE BIT(12) +#define RZN1_WDT_RETRIGGER_ENABLE BIT(13) +#define RZN1_WDT_RETRIGGER_WDSI (0x2 << 14) + +#define RZN1_WDT_PRESCALER 16384 +#define RZN1_WDT_MAX 4095 + +struct rzn1_watchdog { + struct watchdog_device wdt; + void __iomem *base; + unsigned long clk_rate; +}; + +#define to_rzn1_watchdog(_ptr) \ + container_of(_ptr, struct rzn1_watchdog, wdt) + +static inline uint32_t get_max_heart_beat(unsigned long clk_rate) +{ + return (RZN1_WDT_MAX * RZN1_WDT_PRESCALER) / (clk_rate / 1000); +} + +static inline uint32_t compute_reload_value(uint32_t tick_ms, + unsigned long clk_rate) +{ + return (tick_ms * (clk_rate / 1000)) / RZN1_WDT_PRESCALER; +} + +static int rzn1_wdt_ping(struct watchdog_device *w) +{ + struct rzn1_watchdog *wdt = to_rzn1_watchdog(w); + + /* Any value retrigggers the watchdog */ + writel(0, wdt->base + RZN1_WDT_RETRIGGER); + + return 0; +} + +static int rzn1_wdt_start(struct watchdog_device *w) +{ + struct rzn1_watchdog *wdt = to_rzn1_watchdog(w); + u32 val; + + /* + * The hardware allows you to write to this reg only once. + * Since this includes the reload value, there is no way to change the + * timeout once started. Also note that the WDT clock is half the bus + * fabric clock rate, so if the bus fabric clock rate is changed after + * the WDT is started, the WDT interval will be wrong. + */ + val = RZN1_WDT_RETRIGGER_WDSI; + val |= RZN1_WDT_RETRIGGER_ENABLE; + val |= RZN1_WDT_RETRIGGER_PRESCALE; + val |= compute_reload_value(w->max_hw_heartbeat_ms, wdt->clk_rate); + writel(val, wdt->base + RZN1_WDT_RETRIGGER); + + return 0; +} + +static irqreturn_t rzn1_wdt_irq(int irq, void *_wdt) +{ + struct rzn1_watchdog *wdt = (struct rzn1_watchdog *)_wdt; + + dev_info(wdt->wdt.parent, "%s triggered\n", __func__); + return IRQ_HANDLED; +} + +static struct watchdog_info rzn1_wdt_info = { + .identity = "RZ/N1 Watchdog", + .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, +}; + +static const struct watchdog_ops rzn1_wdt_ops = { + .owner = THIS_MODULE, + .start = rzn1_wdt_start, + .ping = rzn1_wdt_ping, +}; + +static const struct watchdog_device rzn1_wdt = { + .info = &rzn1_wdt_info, + .ops = &rzn1_wdt_ops, + .status = WATCHDOG_NOWAYOUT_INIT_STATUS, +}; + +static void rzn1_wdt_clk_disable_unprepare(void *data) +{ + clk_disable_unprepare(data); +} + +static int rzn1_wdt_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rzn1_watchdog *wdt; + struct device_node *np = dev->of_node; + struct clk *clk; + int ret; + int irq; + + wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return -ENOMEM; + + wdt->wdt = rzn1_wdt; + wdt->wdt.parent = dev; + + wdt->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(wdt->base)) + return PTR_ERR(wdt->base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, rzn1_wdt_irq, 0, + np->name, wdt); + if (ret) { + dev_err(dev, "failed to request irq %d\n", irq); + return ret; + } + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get the clock\n"); + return PTR_ERR(clk); + } + + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(dev, "failed to prepare/enable the clock\n"); + return ret; + } + + ret = devm_add_action_or_reset(dev, rzn1_wdt_clk_disable_unprepare, + clk); + if (ret) { + dev_err(dev, "failed to register clock unprepare callback\n"); + return ret; + } + + wdt->clk_rate = clk_get_rate(clk); + if (!wdt->clk_rate) { + dev_err(dev, "failed to get the clock rate\n"); + return -EINVAL; + } + + /* + * The period of the watchdog cannot be changed once set + * and is limited to a very short period. + * Configure it for a 1s period once and for all, and + * rely on the heart-beat provided by the watchdog core + * to make this usable by the user-space. + */ + wdt->wdt.max_hw_heartbeat_ms = get_max_heart_beat(wdt->clk_rate); + if (wdt->wdt.max_hw_heartbeat_ms > 1000) + wdt->wdt.max_hw_heartbeat_ms = 1000; + + wdt->wdt.timeout = DEFAULT_TIMEOUT; + ret = watchdog_init_timeout(&wdt->wdt, 0, dev); + + return devm_watchdog_register_device(dev, &wdt->wdt); +} + + +static const struct of_device_id rzn1_wdt_match[] = { + { .compatible = "renesas,rzn1-wdt" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rzn1_wdt_match); + +static struct platform_driver rzn1_wdt_driver = { + .probe = rzn1_wdt_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = rzn1_wdt_match, + }, +}; + +module_platform_driver(rzn1_wdt_driver); + +MODULE_DESCRIPTION("Renesas RZ/N1 hardware watchdog"); +MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>"); +MODULE_LICENSE("GPL v2"); -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 5/5] watchdog: Add Renesas RZ/N1 Watchdog driver 2022-02-21 9:50 ` [PATCH v3 5/5] watchdog: Add Renesas RZ/N1 Watchdog driver Jean-Jacques Hiblot @ 2022-03-09 8:23 ` Jean-Jacques Hiblot 0 siblings, 0 replies; 4+ messages in thread From: Jean-Jacques Hiblot @ 2022-03-09 8:23 UTC (permalink / raw) To: linux-renesas-soc, geert+renesas, Wim Van Sebroeck, Guenter Roeck Cc: Phil Edworthy, Linux Kernel Mailing List, linux-watchdog Hi Geert, Guenter, What is the status of this patch ? There has been no comment on v3, I had hoped it could go in the next version. Thanks, Jean-Jacques Le lun. 21 févr. 2022 à 10:51, Jean-Jacques Hiblot <jjhiblot@traphandler.com> a écrit : > > From: Phil Edworthy <phil.edworthy@renesas.com> > > This is a driver for the standard WDT on the RZ/N1 devices. This WDT has > very limited timeout capabilities. However, it can reset the device. > To do so, the corresponding bits in the SysCtrl RSTEN register need to > be enabled. This is not done by this driver. > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> > --- > drivers/watchdog/Kconfig | 8 ++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/rzn1_wdt.c | 206 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 215 insertions(+) > create mode 100644 drivers/watchdog/rzn1_wdt.c > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index c8fa79da23b3..ba6e4ebef404 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -883,6 +883,14 @@ config RENESAS_RZAWDT > This driver adds watchdog support for the integrated watchdogs in the > Renesas RZ/A SoCs. These watchdogs can be used to reset a system. > > +config RENESAS_RZN1WDT > + tristate "Renesas RZ/N1 watchdog" > + depends on ARCH_RENESAS || COMPILE_TEST > + select WATCHDOG_CORE > + help > + This driver adds watchdog support for the integrated watchdogs in the > + Renesas RZ/N1 SoCs. These watchdogs can be used to reset a system. > + > config RENESAS_RZG2LWDT > tristate "Renesas RZ/G2L WDT Watchdog" > depends on ARCH_RENESAS || COMPILE_TEST > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index f7da867e8782..38d38564f47b 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -84,6 +84,7 @@ obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o > obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o > obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o > obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o > +obj-$(CONFIG_RENESAS_RZN1WDT) += rzn1_wdt.o > obj-$(CONFIG_RENESAS_RZG2LWDT) += rzg2l_wdt.o > obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o > obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o > diff --git a/drivers/watchdog/rzn1_wdt.c b/drivers/watchdog/rzn1_wdt.c > new file mode 100644 > index 000000000000..7f5884e5d460 > --- /dev/null > +++ b/drivers/watchdog/rzn1_wdt.c > @@ -0,0 +1,206 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Renesas RZ/N1 Watchdog timer. > + * This is a 12-bit timer driver from a (62.5/16384) MHz clock. It can't even > + * cope with 2 seconds. > + * > + * Copyright 2018 Renesas Electronics Europe Ltd. > + * > + * Derived from Ralink RT288x watchdog timer. > + */ > + > +#include <linux/clk.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/watchdog.h> > + > +#define DEFAULT_TIMEOUT 60 > + > +#define RZN1_WDT_RETRIGGER 0x0 > +#define RZN1_WDT_RETRIGGER_RELOAD_VAL 0 > +#define RZN1_WDT_RETRIGGER_RELOAD_VAL_MASK 0xfff > +#define RZN1_WDT_RETRIGGER_PRESCALE BIT(12) > +#define RZN1_WDT_RETRIGGER_ENABLE BIT(13) > +#define RZN1_WDT_RETRIGGER_WDSI (0x2 << 14) > + > +#define RZN1_WDT_PRESCALER 16384 > +#define RZN1_WDT_MAX 4095 > + > +struct rzn1_watchdog { > + struct watchdog_device wdt; > + void __iomem *base; > + unsigned long clk_rate; > +}; > + > +#define to_rzn1_watchdog(_ptr) \ > + container_of(_ptr, struct rzn1_watchdog, wdt) > + > +static inline uint32_t get_max_heart_beat(unsigned long clk_rate) > +{ > + return (RZN1_WDT_MAX * RZN1_WDT_PRESCALER) / (clk_rate / 1000); > +} > + > +static inline uint32_t compute_reload_value(uint32_t tick_ms, > + unsigned long clk_rate) > +{ > + return (tick_ms * (clk_rate / 1000)) / RZN1_WDT_PRESCALER; > +} > + > +static int rzn1_wdt_ping(struct watchdog_device *w) > +{ > + struct rzn1_watchdog *wdt = to_rzn1_watchdog(w); > + > + /* Any value retrigggers the watchdog */ > + writel(0, wdt->base + RZN1_WDT_RETRIGGER); > + > + return 0; > +} > + > +static int rzn1_wdt_start(struct watchdog_device *w) > +{ > + struct rzn1_watchdog *wdt = to_rzn1_watchdog(w); > + u32 val; > + > + /* > + * The hardware allows you to write to this reg only once. > + * Since this includes the reload value, there is no way to change the > + * timeout once started. Also note that the WDT clock is half the bus > + * fabric clock rate, so if the bus fabric clock rate is changed after > + * the WDT is started, the WDT interval will be wrong. > + */ > + val = RZN1_WDT_RETRIGGER_WDSI; > + val |= RZN1_WDT_RETRIGGER_ENABLE; > + val |= RZN1_WDT_RETRIGGER_PRESCALE; > + val |= compute_reload_value(w->max_hw_heartbeat_ms, wdt->clk_rate); > + writel(val, wdt->base + RZN1_WDT_RETRIGGER); > + > + return 0; > +} > + > +static irqreturn_t rzn1_wdt_irq(int irq, void *_wdt) > +{ > + struct rzn1_watchdog *wdt = (struct rzn1_watchdog *)_wdt; > + > + dev_info(wdt->wdt.parent, "%s triggered\n", __func__); > + return IRQ_HANDLED; > +} > + > +static struct watchdog_info rzn1_wdt_info = { > + .identity = "RZ/N1 Watchdog", > + .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, > +}; > + > +static const struct watchdog_ops rzn1_wdt_ops = { > + .owner = THIS_MODULE, > + .start = rzn1_wdt_start, > + .ping = rzn1_wdt_ping, > +}; > + > +static const struct watchdog_device rzn1_wdt = { > + .info = &rzn1_wdt_info, > + .ops = &rzn1_wdt_ops, > + .status = WATCHDOG_NOWAYOUT_INIT_STATUS, > +}; > + > +static void rzn1_wdt_clk_disable_unprepare(void *data) > +{ > + clk_disable_unprepare(data); > +} > + > +static int rzn1_wdt_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rzn1_watchdog *wdt; > + struct device_node *np = dev->of_node; > + struct clk *clk; > + int ret; > + int irq; > + > + wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); > + if (!wdt) > + return -ENOMEM; > + > + wdt->wdt = rzn1_wdt; > + wdt->wdt.parent = dev; > + > + wdt->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(wdt->base)) > + return PTR_ERR(wdt->base); > + > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) > + return irq; > + > + ret = devm_request_irq(dev, irq, rzn1_wdt_irq, 0, > + np->name, wdt); > + if (ret) { > + dev_err(dev, "failed to request irq %d\n", irq); > + return ret; > + } > + > + clk = devm_clk_get(dev, NULL); > + if (IS_ERR(clk)) { > + dev_err(dev, "failed to get the clock\n"); > + return PTR_ERR(clk); > + } > + > + ret = clk_prepare_enable(clk); > + if (ret) { > + dev_err(dev, "failed to prepare/enable the clock\n"); > + return ret; > + } > + > + ret = devm_add_action_or_reset(dev, rzn1_wdt_clk_disable_unprepare, > + clk); > + if (ret) { > + dev_err(dev, "failed to register clock unprepare callback\n"); > + return ret; > + } > + > + wdt->clk_rate = clk_get_rate(clk); > + if (!wdt->clk_rate) { > + dev_err(dev, "failed to get the clock rate\n"); > + return -EINVAL; > + } > + > + /* > + * The period of the watchdog cannot be changed once set > + * and is limited to a very short period. > + * Configure it for a 1s period once and for all, and > + * rely on the heart-beat provided by the watchdog core > + * to make this usable by the user-space. > + */ > + wdt->wdt.max_hw_heartbeat_ms = get_max_heart_beat(wdt->clk_rate); > + if (wdt->wdt.max_hw_heartbeat_ms > 1000) > + wdt->wdt.max_hw_heartbeat_ms = 1000; > + > + wdt->wdt.timeout = DEFAULT_TIMEOUT; > + ret = watchdog_init_timeout(&wdt->wdt, 0, dev); > + > + return devm_watchdog_register_device(dev, &wdt->wdt); > +} > + > + > +static const struct of_device_id rzn1_wdt_match[] = { > + { .compatible = "renesas,rzn1-wdt" }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, rzn1_wdt_match); > + > +static struct platform_driver rzn1_wdt_driver = { > + .probe = rzn1_wdt_probe, > + .driver = { > + .name = KBUILD_MODNAME, > + .of_match_table = rzn1_wdt_match, > + }, > +}; > + > +module_platform_driver(rzn1_wdt_driver); > + > +MODULE_DESCRIPTION("Renesas RZ/N1 hardware watchdog"); > +MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>"); > +MODULE_LICENSE("GPL v2"); > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-03-09 8:24 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-02-21 9:50 [PATCH v3 0/5] ARM: r9a06g032: add support for the watchdogs Jean-Jacques Hiblot 2022-02-21 9:50 ` [PATCH v3 2/5] dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1 Jean-Jacques Hiblot 2022-02-21 9:50 ` [PATCH v3 5/5] watchdog: Add Renesas RZ/N1 Watchdog driver Jean-Jacques Hiblot 2022-03-09 8:23 ` Jean-Jacques Hiblot
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