* [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support
@ 2025-09-12 12:07 Michael Walle
2025-09-12 12:07 ` [PATCH v2 1/7] dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module Michael Walle
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare,
Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon,
linux-watchdog, Andrew Davis
Now that the PMIC support is there, we can finally, upstream the
support for this board. Besides the usual device tree, this
patchset contains the support for the on-board house keeping MCU. It
make extensive reuse of the drivers for the former SMARC-sAL28
board. Besides different hwmon sensors, all the dt binding patches
will just add a board specific compatible (in addition to the old
sl28 compatible) to make any future board specific quirks possible.
I'm aware that there is a patch [1] which moves the sl28cpld MFD
schema to a different directory. Once that patch is merged, I'll
repost this series. But I already want to get some early feedback.
v2:
- dropped patches which were already picked up
- new patch "dt-bindings: mfd: tps6594: allow gpio-line-names"
- separate driver for the hwmon, add missing hwmon documentation,
thanks Guenter
- split the DT as suggested by the SoC maintainers
- add missing copyright and license to the overlays, thanks Andrew
Michael Walle (7):
dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module
dt-bindings: mfd: tps6594: allow gpio-line-names
arm64: dts: ti: Add support for Kontron SMARC-sAM67
dt-bindings: hwmon: sl28cpld: add sa67mcu compatible
dt-bindings: watchdog: add SMARC-sAM67 support
hwmon: add SMARC-sAM67 support
arm64: dts: ti: sa67: add on-board management controller node
.../devicetree/bindings/arm/ti/k3.yaml | 1 +
.../hwmon/kontron,sl28cpld-hwmon.yaml | 1 +
.../devicetree/bindings/mfd/ti,tps6594.yaml | 1 +
.../watchdog/kontron,sl28cpld-wdt.yaml | 7 +-
Documentation/hwmon/sa67.rst | 41 +
MAINTAINERS | 1 +
arch/arm64/boot/dts/ti/Makefile | 6 +
.../dts/ti/k3-am67a-kontron-sa67-base.dts | 1091 +++++++++++++++++
.../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso | 26 +
.../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso | 31 +
drivers/hwmon/Kconfig | 10 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/sa67mcu-hwmon.c | 161 +++
13 files changed, 1377 insertions(+), 1 deletion(-)
create mode 100644 Documentation/hwmon/sa67.rst
create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso
create mode 100644 drivers/hwmon/sa67mcu-hwmon.c
--
2.39.5
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v2 1/7] dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle @ 2025-09-12 12:07 ` Michael Walle 2025-09-12 12:07 ` [PATCH v2 2/7] dt-bindings: mfd: tps6594: allow gpio-line-names Michael Walle ` (6 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw) To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare, Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis, Krzysztof Kozlowski Add devicetree bindings for the AM67 based Kontron SMARC-sAM67 module. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index e80c653fa438..af41f1541850 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -181,6 +181,7 @@ properties: items: - enum: - beagle,am67a-beagley-ai + - kontron,sa67 # Kontron SMARC-sAM67 board - ti,j722s-evm - const: ti,j722s -- 2.39.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/7] dt-bindings: mfd: tps6594: allow gpio-line-names 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle 2025-09-12 12:07 ` [PATCH v2 1/7] dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module Michael Walle @ 2025-09-12 12:07 ` Michael Walle 2025-09-15 21:34 ` Rob Herring (Arm) 2025-09-12 12:07 ` [PATCH v2 3/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67 Michael Walle ` (5 subsequent siblings) 7 siblings, 1 reply; 14+ messages in thread From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw) To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare, Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis Setting the signal names in the device tree was already possible, but it will lead to a warning. Allow the gpio-line-names property to fix that. Signed-off-by: Michael Walle <mwalle@kernel.org> --- Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml index a48cb00afe43..ca17fbdea691 100644 --- a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml @@ -41,6 +41,7 @@ properties: system-power-controller: true gpio-controller: true + gpio-line-names: true '#gpio-cells': const: 2 -- 2.39.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: mfd: tps6594: allow gpio-line-names 2025-09-12 12:07 ` [PATCH v2 2/7] dt-bindings: mfd: tps6594: allow gpio-line-names Michael Walle @ 2025-09-15 21:34 ` Rob Herring (Arm) 0 siblings, 0 replies; 14+ messages in thread From: Rob Herring (Arm) @ 2025-09-15 21:34 UTC (permalink / raw) To: Michael Walle Cc: linux-watchdog, Guenter Roeck, linux-kernel, Wim Van Sebroeck, Krzysztof Kozlowski, Jean Delvare, Vignesh Raghavendra, Lee Jones, linux-arm-kernel, Andrew Davis, linux-hwmon, Tero Kristo, devicetree, Conor Dooley, Nishanth Menon, Srinivas Kandagatla On Fri, 12 Sep 2025 14:07:40 +0200, Michael Walle wrote: > Setting the signal names in the device tree was already possible, but > it will lead to a warning. Allow the gpio-line-names property to fix > that. > > Signed-off-by: Michael Walle <mwalle@kernel.org> > --- > Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle 2025-09-12 12:07 ` [PATCH v2 1/7] dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module Michael Walle 2025-09-12 12:07 ` [PATCH v2 2/7] dt-bindings: mfd: tps6594: allow gpio-line-names Michael Walle @ 2025-09-12 12:07 ` Michael Walle 2025-09-12 12:07 ` [PATCH v2 4/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible Michael Walle ` (4 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw) To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare, Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis Add device tree support for the Kontron SMARC-sAM67 module, which is based on a TI AM67A SoC. The module features: * Quad-core AM67A94 at 1.4GHz with 8 GiB RAM * 64 GiB eMMC, 4 MiB SPI flash for failsafe booting * Dedicated RTC * Multiple interfaces: 4x UART, 2x USB 2.0/USB 3.2, 2x GBE, QSPI, 7x I2C, * Display support: 2x LVDS, 1x DSI (*), 1x DP (*) * Camera support: 4x CSI (*) * Onboard microcontroller for boot control, failsafe booting and external watchdog (*) not yet supported by the kernel There is a base device tree and overlays which will add optional features. At the moment there is one full featured variant of that board whose device tree is generated during build by merging all the device tree overlays. Signed-off-by: Michael Walle <mwalle@kernel.org> --- arch/arm64/boot/dts/ti/Makefile | 6 + .../dts/ti/k3-am67a-kontron-sa67-base.dts | 1073 +++++++++++++++++ .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso | 26 + .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso | 31 + 4 files changed, 1136 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index aad9177930e6..7047d3421783 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -133,7 +133,13 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo # Boards with J722s SoC +k3-am67a-kontron-sa67-dtbs := k3-am67a-kontron-sa67-base.dtb \ + k3-am67a-kontron-sa67-rtc-rv8263.dtbo k3-am67a-kontron-sa67-gbe1.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-base.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-gbe1.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-rtc-rv8263.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts new file mode 100644 index 000000000000..5755df689752 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -0,0 +1,1073 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Kontron SMARC-sAM67 module + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> +#include "k3-j722s.dtsi" +#include "k3-serdes.h" + +/ { + compatible = "kontron,sa67", "ti,j722s"; + model = "Kontron SMARC-sAM67"; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart0; + serial2 = &main_uart5; + serial3 = &wkup_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &wkup_rtc0; + }; + + lcd0_backlight: backlight-1 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_backlight_pins_default>; + pwms = <&epwm1 0 50000 0>; + brightness-levels = <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + enable-gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + lcd1_backlight: backlight-2 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_backlight_pins_default>; + pwms = <&epwm1 1 50000 0>; + brightness-levels = <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + enable-gpios = <&main_gpio1 18 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + connector-1 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_connector_pins_default>; + type = "micro"; + id-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + vbus-supply = <&vcc_usb0_vbus>; + + port { + usb0_connector: endpoint { + remote-endpoint = <&usb0_hc>; + }; + }; + + }; + + memory@80000000 { + /* Filled in by bootloader */ + reg = <0x00000000 0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000000 0x00000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x10000000>; + alignment = <0x2000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + }; + + vin_5p0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "V_3V0_5V25_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s5: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_1p8_s5: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s0: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3p3_s5>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&tps652g1 1 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_s0: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "SDIO_PWR_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3p3_sd_s0_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_vio_s0: regulator-6 { + compatible = "regulator-gpio"; + regulator-name = "V_3V3_1V8_SD_S0"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3p3_sd_vio_s0_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3p3_s0>; + regulator-boot-on; + enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0>, + <1800000 0x1>; + bootph-all; + }; + + vcc_3p3_cam_s0: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_CAM_S0"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3p3_cam_s0_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3p3_s5>; + enable-active-high; + interrupts-extended = <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>; + bootph-all; + }; + + vcc_1p1_s0: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V1_S0"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_1p1_s3>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + /* shared with V_0V75_0V85_CORE_S0 */ + gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_0p85_vcore_s0: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "V_0V75_0V85_CORE_S0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_lcd0_panel: regulator-10 { + compatible = "regulator-fixed"; + regulator-name = "LCD0_VDD_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_lcd0_panel_pins_default>; + enable-active-high; + gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + vcc_lcd1_panel: regulator-11 { + compatible = "regulator-fixed"; + regulator-name = "LCD1_VDD_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_lcd1_panel_pins_default>; + enable-active-high; + gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + }; + + vcc_usb0_vbus: regulator-12 { + compatible = "regulator-fixed"; + regulator-name = "USB0_EN_OC#"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_usb0_vbus_pins_default>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + }; +}; + +&audio_refclk0 { + pinctrl-names = "default"; + pinctrl-0 = <&audio_refclk0_pins_default>; + status = "disabled"; +}; + +&audio_refclk1 { + pinctrl-names = "default"; + pinctrl-0 = <&audio_refclk1_pins_default>; + status = "disabled"; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw3g_pins_default>, <&rgmii1_pins_default>, + <&rgmii2_pins_default>; + status = "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw3g_mdio_pins_default>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-connection-type = "rgmii-id"; + phy-handle = <&phy0>; + nvmem-cells = <&base_mac_address 0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&main_gpio0 { + gpio-line-names = + "", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL", + "RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#", + "QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2", + "BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "", + "", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE", + "CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#", + "EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "", + "", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "", + "CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11", + "SLEEP#", "LID#"; + + bootph-all; + status = "okay"; +}; + +&main_gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "", + "GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN", + "LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "", + "GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "", + "USB0_DRVVBUS", "USB1_DRVVBUS"; + + bootph-all; + status = "okay"; +}; + +/* I2C_LOCAL */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <100000>; + bootph-all; + status = "okay"; + + tps652g1: pmic@44 { + compatible = "ti,tps652g1"; + reg = <0x44>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#", + "EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupts-extended = <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>; + + buck1-supply = <&vin_5p0>; + buck2-supply = <&vin_5p0>; + buck3-supply = <&vin_5p0>; + buck4-supply = <&vin_5p0>; + ldo1-supply = <&vin_5p0>; + ldo2-supply = <&vin_5p0>; + ldo3-supply = <&vin_5p0>; + + bootph-all; + + regulators { + vcc_0p85_s0: buck1 { + regulator-name = "V_0V85_S0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p1_s3: buck2 { + regulator-name = "V_1V1_S3"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s0: buck3 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p2_s0: buck4 { + regulator-name = "V_1V2_S0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_vda_pll_s0: ldo1 { + regulator-name = "V_1V8_VDA_PLL_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s3: ldo2 { + regulator-name = "V_1V8_S3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_ret_s5: ldo3 { + regulator-name = "V_1V8_RET_S5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + rtc: rtc@51 { + compatible = "microcrystal,rv8263"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins_default>; + interrupts-extended = <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +/* I2C_CAM */ +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <100000>; + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_mux_pins_default>; + + vdd-supply = <&vcc_1p8_s0>; + reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>; + + i2c_cam0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_cam1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_cam2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_cam3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +/* I2C_LCD */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_pmx0 { + audio_refclk0_pins_default: audio-refclk0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0c4, PIN_OUTPUT, 5) /* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ + >; + }; + + audio_refclk1_pins_default: audio-refclk1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + + cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x15c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + cpsw3g_pins_default: cpsw3g-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1b8, PIN_OUTPUT, 1) /* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_COMP */ + >; + }; + + edp_bridge_pins_default: edp-bridge-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x098, PIN_OUTPUT, 7) /* (V21) GPMC0_WAIT0.GPIO0_37 */ + J722S_IOPAD(0x09c, PIN_INPUT, 7) /* (W26) GPMC0_WAIT1.GPIO0_38 */ + >; + }; + + i2c_mux_pins_default: i2c-mux-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x028, PIN_OUTPUT, 7) /* (M27) OSPI0_D7.GPIO0_10 */ + >; + }; + + lcd0_backlight_pins_default: lcd0-backlight-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x074, PIN_OUTPUT, 7) /* (V22) GPMC0_AD14.GPIO0_29 */ + J722S_IOPAD(0x110, PIN_OUTPUT, 4) /* (G27) MMC2_DAT1.EHRPWM1_A */ + >; + }; + + lcd1_backlight_pins_default: lcd1-backlight-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (E19) SPI0_D0.GPIO1_18 */ + J722S_IOPAD(0x114, PIN_OUTPUT, 4) /* (G26) MMC2_DAT0.EHRPWM1_B */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1e0, PIN_INPUT, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x1e4, PIN_INPUT, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0b0, PIN_INPUT, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x0b4, PIN_INPUT, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1d0, PIN_INPUT, 2) /* (E22) UART0_CTSn.I2C3_SCL */ + J722S_IOPAD(0x1d4, PIN_INPUT, 2) /* (B21) UART0_RTSn.I2C3_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0a8, PIN_INPUT, 1) /* (R27) GPMC0_CSn0.I2C4_SCL */ + J722S_IOPAD(0x0ac, PIN_INPUT, 1) /* (P21) GPMC0_CSn1.I2C4_SDA */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1c8, PIN_INPUT, 0) /* (F19) UART0_RXD */ + J722S_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (F20) UART0_TXD */ + >; + bootph-all; + }; + + main_uart5_pins_default: main-uart5-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x108, PIN_INPUT, 3) /* (J27) MMC2_DAT3.UART5_RXD */ + J722S_IOPAD(0x10c, PIN_OUTPUT, 3) /* (H27) MMC2_DAT2.UART5_TXD */ + J722S_IOPAD(0x008, PIN_INPUT, 5) /* (L22) OSPI0_DQS.UART5_CTSn */ + J722S_IOPAD(0x004, PIN_OUTPUT, 5) /* (L23) OSPI0_LBCLKO.UART5_RTSn */ + >; + }; + + mcasp0_pins_default: mcasp0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1a4, PIN_INPUT, 0) /* (D25) MCASP0_ACLKX */ + J722S_IOPAD(0x1a8, PIN_INPUT, 0) /* (C26) MCASP0_AFSX */ + J722S_IOPAD(0x1a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ + J722S_IOPAD(0x19c, PIN_OUTPUT, 0) /* (B25) MCASP0_AXR1 */ + >; + }; + + mcasp2_pins_default: mcasp2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x070, PIN_INPUT, 3) /* (V24) GPMC0_AD13.MCASP2_ACLKX */ + J722S_IOPAD(0x06c, PIN_INPUT, 3) /* (V26) GPMC0_AD12.MCASP2_AFSX */ + J722S_IOPAD(0x05c, PIN_INPUT, 3) /* (U27) GPMC0_AD8.MCASP2_AXR0 */ + J722S_IOPAD(0x060, PIN_OUTPUT, 3) /* (U26) GPMC0_AD9.MCASP2_AXR1 */ + >; + }; + + oldi0_pins_default: oldi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x260, PIN_OUTPUT, 0) /* (AF23) OLDI0_A0N */ + J722S_IOPAD(0x25c, PIN_OUTPUT, 0) /* (AG24) OLDI0_A0P */ + J722S_IOPAD(0x268, PIN_OUTPUT, 0) /* (AG22) OLDI0_A1N */ + J722S_IOPAD(0x264, PIN_OUTPUT, 0) /* (AG23) OLDI0_A1P */ + J722S_IOPAD(0x270, PIN_OUTPUT, 0) /* (AB20) OLDI0_A2N */ + J722S_IOPAD(0x26c, PIN_OUTPUT, 0) /* (AB21) OLDI0_A2P */ + J722S_IOPAD(0x278, PIN_OUTPUT, 0) /* (AG20) OLDI0_A3N */ + J722S_IOPAD(0x274, PIN_OUTPUT, 0) /* (AG21) OLDI0_A3P */ + J722S_IOPAD(0x2a0, PIN_OUTPUT, 0) /* (AF21) OLDI0_CLK0N */ + J722S_IOPAD(0x29c, PIN_OUTPUT, 0) /* (AE20) OLDI0_CLK0P */ + >; + }; + + oldi1_pins_default: oldi1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x280, PIN_OUTPUT, 0) /* (AD21) OLDI0_A4N */ + J722S_IOPAD(0x27c, PIN_OUTPUT, 0) /* (AC21) OLDI0_A4P */ + J722S_IOPAD(0x288, PIN_OUTPUT, 0) /* (AF19) OLDI0_A5N */ + J722S_IOPAD(0x284, PIN_OUTPUT, 0) /* (AF18) OLDI0_A5P */ + J722S_IOPAD(0x290, PIN_OUTPUT, 0) /* (AG17) OLDI0_A6N */ + J722S_IOPAD(0x28c, PIN_OUTPUT, 0) /* (AG18) OLDI0_A6P */ + J722S_IOPAD(0x298, PIN_OUTPUT, 0) /* (AB19) OLDI0_A7N */ + J722S_IOPAD(0x294, PIN_OUTPUT, 0) /* (AA20) OLDI0_A7P */ + J722S_IOPAD(0x2a8, PIN_OUTPUT, 0) /* (AD20) OLDI0_CLK1N */ + J722S_IOPAD(0x2a4, PIN_OUTPUT, 0) /* (AE19) OLDI0_CLK1P */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x02c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x030, PIN_OUTPUT, 0) /* (K23) OSPI0_CSn1 */ + J722S_IOPAD(0x034, PIN_OUTPUT, 0) /* (K22) OSPI0_CSn2 */ + J722S_IOPAD(0x00c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + >; + bootph-all; + }; + + pcie0_rc_pins_default: pcie0-rc-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x2ac, PIN_OUTPUT, 0) /* (F25) PCIE0_CLKREQn */ + J722S_IOPAD(0x1b4, PIN_OUTPUT, 7) /* (B20) SPI0_CS0.GPIO1_15 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x090, PIN_INPUT, 7) /* (P27) GPMC0_BE0n_CLE.GPIO0_35 */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x14c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0f8, PIN_INPUT, 2) /* (AB24) VOUT0_HSYNC.RGMII2_RD0 */ + J722S_IOPAD(0x0fc, PIN_INPUT, 2) /* (AC27) VOUT0_DE.RGMII2_RD1 */ + J722S_IOPAD(0x100, PIN_INPUT, 2) /* (AB23) VOUT0_VSYNC.RGMII2_RD2 */ + J722S_IOPAD(0x104, PIN_INPUT, 2) /* (AC26) VOUT0_PCLK.RGMII2_RD3 */ + J722S_IOPAD(0x0f4, PIN_INPUT, 2) /* (AB27) VOUT0_DATA15.RGMII2_RXC */ + J722S_IOPAD(0x0f0, PIN_INPUT, 2) /* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */ + J722S_IOPAD(0x0e0, PIN_OUTPUT, 2) /* (AA25) VOUT0_DATA10.RGMII2_TD0 */ + J722S_IOPAD(0x0e4, PIN_OUTPUT, 2) /* (AB25) VOUT0_DATA11.RGMII2_TD1 */ + J722S_IOPAD(0x0e8, PIN_OUTPUT, 2) /* (AA23) VOUT0_DATA12.RGMII2_TD2 */ + J722S_IOPAD(0x0ec, PIN_OUTPUT, 2) /* (AA22) VOUT0_DATA13.RGMII2_TD3 */ + J722S_IOPAD(0x0dc, PIN_OUTPUT, 2) /* (AA27) VOUT0_DATA9.RGMII2_TXC */ + J722S_IOPAD(0x0d8, PIN_OUTPUT, 2) /* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */ + >; + }; + + rtc_pins_default: rtc-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 */ + >; + }; + + sdhci1_pins_default: sdhci1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x23c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x22c, PIN_INPUT, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x228, PIN_INPUT, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + J722S_IOPAD(0x244, PIN_INPUT, 0) /* (A24) MMC1_SDWP */ + >; + bootph-all; + }; + + usb0_connector_pins_default: usb0-connector-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7) /* (N23) GPMC0_WEn.GPIO0_34 */ + >; + }; + + usb1_pins_default: usb1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x258, PIN_OUTPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; + + vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01c, PIN_OUTPUT, 7) /* (L21) OSPI0_D4.GPIO0_7 */ + >; + bootph-all; + }; + + vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x020, PIN_OUTPUT, 7) /* (M26) OSPI0_D5.GPIO0_8 */ + >; + bootph-all; + }; + + vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1f0, PIN_OUTPUT, 7) /* (A23) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x078, PIN_OUTPUT, 7) /* (V23) GPMC0_AD15.GPIO0_30 */ + >; + }; + + vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (E20) SPI0_D1.GPIO1_19 */ + >; + }; + + vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ + >; + }; +}; + +/* SER1 */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; + status = "okay"; +}; + +/* SER2 */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart5_pins_default>; + bootph-all; + status = "okay"; +}; + +/* I2S0 */ +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins_default>; + op-mode = <0>; /* I2S */ + tdm-slots = <2>; + serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* I2S2 */ +&mcasp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp2_pins_default>; + op-mode = <0>; /* I2S */ + tdm-slots = <2>; + serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* CAN0 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + status = "okay"; +}; + +/* CAN1 */ +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + status = "okay"; +}; + +&mcu_gpio0 { + gpio-line-names = + "", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12", + "MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13"; +}; + +/* I2C_GP */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <100000>; + status = "okay"; + + /* SMARC Module EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&vcc_1p8_s0>; + }; +}; + +&mcu_pmx0 { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ + J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ + >; + }; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ + J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ + J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /* (C1) MCU_MCAN1_TX */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x014, PIN_INPUT, 0) /* (B8) MCU_UART0_RXD */ + J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0) /* (B4) MCU_UART0_TXD */ + J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0) /* (B5) MCU_UART0_CTSn */ + J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0) /* (C5) MCU_UART0_RTSn */ + >; + bootph-all; + }; + + mcu_spi0_pins_default: mcu-spi0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0) /* (A9) MCU_SPI0_CLK */ + J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0) /* (C12) MCU_SPI0_CS0 */ + J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0) /* (A10) MCU_SPI0_CS1 */ + J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0) /* (B12) MCU_SPI0_D0 */ + J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0) /* (C11) MCU_SPI0_D1 */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B3) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0) /* (B9) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT, 0) /* (D11) WKUP_I2C0_SDA */ + >; + }; +}; + +/* SPI0 */ +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; +}; + +/* SER0 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; + status = "okay"; +}; + +/* QSPI0 */ +&ospi0 { + pinctrl-0 = <&ospi0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + m25p,fast-read; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <3>; + vcc-supply = <&vcc_1p8_s0>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x000000 0x400000>; + label = "failsafe bootloader"; + read-only; + }; + }; + + otp-1 { + compatible = "user-otp"; + + nvmem-layout { + compatible = "kontron,sa67-vpd", "kontron,sl28-vpd"; + + serial_number: serial-number { + }; + + base_mac_address: base-mac-address { + #nvmem-cell-cells = <1>; + }; + }; + }; + }; +}; + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_rc_pins_default>; + + /* + * This is low active, but the driver itself is broken and already + * inverts the logic. + */ + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie>; + phy-names = "pcie-phy"; + status = "okay"; +}; + +&sdhci0 { + disable-wp; + bootph-all; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* SDIO */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci1_pins_default>; + vmmc-supply = <&vcc_3p3_sd_s0>; + vqmmc-supply = <&vcc_3p3_sd_vio_s0>; + bootph-all; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <100>; + ti,fails-without-test-cd; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +&serdes_ln_ctrl { + idle-states = <J722S_SERDES0_LANE0_USB>, + <J722S_SERDES1_LANE0_PCIE0_LANE0>; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&serdes0 { + serdes0_usb3: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + cdns,num-lanes = <1>; + cdns,phy-type = <PHY_TYPE_USB3>; + }; +}; + +&serdes1 { + serdes1_pcie: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz1 1>; + cdns,num-lanes = <1>; + cdns,phy-type = <PHY_TYPE_PCIE>; + }; +}; + +&usb0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + port { + usb0_hc: endpoint { + remote-endpoint = <&usb0_connector>; + }; + }; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; + + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb3>; + phy-names = "cdns3,usb3-phy"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +/* I2C_PM */ +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* SER3 */ +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso new file mode 100644 index 000000000000..5dfb0b8f10d2 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Second ethernet port GBE1. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +&cpsw3g_mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port2 { + phy-connection-type = "rgmii-id"; + phy-handle = <&phy1>; + nvmem-cells = <&base_mac_address 1>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso new file mode 100644 index 000000000000..0a3e9f614c4c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Microcrystal RV8263 RTC variant. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/interrupt-controller/irq.h> + +&{/} { + aliases { + rtc0 = "/bus@f0000/i2c@20000000/rtc@51"; /* &rtc */ + rtc1 = "/bus@f0000/bus@b00000/rtc@2b1f0000"; /* &wkup_rtc0 */ + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + rtc: rtc@51 { + compatible = "microcrystal,rv8263"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins_default>; + interrupts-extended = <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; + }; +}; -- 2.39.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle ` (2 preceding siblings ...) 2025-09-12 12:07 ` [PATCH v2 3/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67 Michael Walle @ 2025-09-12 12:07 ` Michael Walle 2025-09-24 16:00 ` Guenter Roeck 2025-09-12 12:07 ` [PATCH v2 5/7] dt-bindings: watchdog: add SMARC-sAM67 support Michael Walle ` (3 subsequent siblings) 7 siblings, 1 reply; 14+ messages in thread From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw) To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare, Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis, Krzysztof Kozlowski The Kontron SMARC-sAM67 module features an on-board house keeping uC. It is designed to be compatible with the older sl28cpld implementation, but has different sensors, like voltage and temperature monitoring. Add a new compatible for that board. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml index 5803a1770cad..966b221b6caa 100644 --- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml +++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - kontron,sa67mcu-hwmon - kontron,sl28cpld-fan reg: -- 2.39.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible 2025-09-12 12:07 ` [PATCH v2 4/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible Michael Walle @ 2025-09-24 16:00 ` Guenter Roeck 0 siblings, 0 replies; 14+ messages in thread From: Guenter Roeck @ 2025-09-24 16:00 UTC (permalink / raw) To: Michael Walle Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean Delvare, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck, linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis, Krzysztof Kozlowski On Fri, Sep 12, 2025 at 02:07:42PM +0200, Michael Walle wrote: > The Kontron SMARC-sAM67 module features an on-board house keeping uC. > It is designed to be compatible with the older sl28cpld implementation, > but has different sensors, like voltage and temperature monitoring. Add > a new compatible for that board. > > Signed-off-by: Michael Walle <mwalle@kernel.org> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Applied. Guenter ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 5/7] dt-bindings: watchdog: add SMARC-sAM67 support 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle ` (3 preceding siblings ...) 2025-09-12 12:07 ` [PATCH v2 4/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible Michael Walle @ 2025-09-12 12:07 ` Michael Walle 2025-09-24 15:59 ` Guenter Roeck 2025-09-12 12:07 ` [PATCH v2 6/7] hwmon: " Michael Walle ` (2 subsequent siblings) 7 siblings, 1 reply; 14+ messages in thread From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw) To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare, Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis, Krzysztof Kozlowski The SMARC-sAM67 board has an on-board uC which has the same register interface as the older CPLD implementation on the SMARC-sAL28 board. Although the MCU emulates the same behavior, be prepared for any quirks and add a board specific compatible. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml index 872a8471ef65..0821ba0e84a3 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -18,7 +18,12 @@ allOf: properties: compatible: - const: kontron,sl28cpld-wdt + oneOf: + - items: + - enum: + - kontron,sa67mcu-wdt + - const: kontron,sl28cpld-wdt + - const: kontron,sl28cpld-wdt reg: maxItems: 1 -- 2.39.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] dt-bindings: watchdog: add SMARC-sAM67 support 2025-09-12 12:07 ` [PATCH v2 5/7] dt-bindings: watchdog: add SMARC-sAM67 support Michael Walle @ 2025-09-24 15:59 ` Guenter Roeck 0 siblings, 0 replies; 14+ messages in thread From: Guenter Roeck @ 2025-09-24 15:59 UTC (permalink / raw) To: Michael Walle Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean Delvare, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck, linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis, Krzysztof Kozlowski On Fri, Sep 12, 2025 at 02:07:43PM +0200, Michael Walle wrote: > The SMARC-sAM67 board has an on-board uC which has the same register > interface as the older CPLD implementation on the SMARC-sAL28 board. > Although the MCU emulates the same behavior, be prepared for any quirks > and add a board specific compatible. > > Signed-off-by: Michael Walle <mwalle@kernel.org> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > .../devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml > index 872a8471ef65..0821ba0e84a3 100644 > --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml > +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml > @@ -18,7 +18,12 @@ allOf: > > properties: > compatible: > - const: kontron,sl28cpld-wdt > + oneOf: > + - items: > + - enum: > + - kontron,sa67mcu-wdt > + - const: kontron,sl28cpld-wdt > + - const: kontron,sl28cpld-wdt > > reg: > maxItems: 1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 6/7] hwmon: add SMARC-sAM67 support 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle ` (4 preceding siblings ...) 2025-09-12 12:07 ` [PATCH v2 5/7] dt-bindings: watchdog: add SMARC-sAM67 support Michael Walle @ 2025-09-12 12:07 ` Michael Walle 2025-09-24 16:01 ` Guenter Roeck 2025-09-12 12:07 ` [PATCH v2 7/7] arm64: dts: ti: sa67: add on-board management controller node Michael Walle 2025-09-25 7:28 ` [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle 7 siblings, 1 reply; 14+ messages in thread From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw) To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare, Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis Add a new driver for the Kontron SMARC-sAM67 board management controller. It has two voltage sensors and one temperature sensor. Signed-off-by: Michael Walle <mwalle@kernel.org> --- Documentation/hwmon/sa67.rst | 41 +++++++++ MAINTAINERS | 1 + drivers/hwmon/Kconfig | 10 +++ drivers/hwmon/Makefile | 1 + drivers/hwmon/sa67mcu-hwmon.c | 161 ++++++++++++++++++++++++++++++++++ 5 files changed, 214 insertions(+) create mode 100644 Documentation/hwmon/sa67.rst create mode 100644 drivers/hwmon/sa67mcu-hwmon.c diff --git a/Documentation/hwmon/sa67.rst b/Documentation/hwmon/sa67.rst new file mode 100644 index 000000000000..029c7c169b7f --- /dev/null +++ b/Documentation/hwmon/sa67.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +Kernel driver sa67mcu +===================== + +Supported chips: + + * Kontron sa67mcu + + Prefix: 'sa67mcu' + + Datasheet: not available + +Authors: Michael Walle <mwalle@kernel.org> + +Description +----------- + +The sa67mcu is a board management controller which also exposes a hardware +monitoring controller. + +The controller has two voltage and one temperature sensor. The values are +hold in two 8 bit registers to form one 16 bit value. Reading the lower byte +will also capture the high byte to make the access atomic. The unit of the +volatge sensors are 1mV and the unit of the temperature sensor is 0.1degC. + +Sysfs entries +------------- + +The following attributes are supported. + +======================= ======================================================== +in0_label "VDDIN" +in0_input Measured VDDIN voltage. + +in1_label "VDD_RTC" +in1_input Measured VDD_RTC voltage. + +temp1_input MCU temperature. Roughly the board temperature. +======================= ======================================================== + diff --git a/MAINTAINERS b/MAINTAINERS index fa7f80bd7b2f..69fcd5c077ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23489,6 +23489,7 @@ F: Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc. F: Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml F: Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml F: drivers/gpio/gpio-sl28cpld.c +F: drivers/hwmon/sa67mcu-hwmon.c F: drivers/hwmon/sl28cpld-hwmon.c F: drivers/irqchip/irq-sl28cpld.c F: drivers/pwm/pwm-sl28cpld.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index d6769288a76e..c2f288ebdf44 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1905,6 +1905,16 @@ config SENSORS_RASPBERRYPI_HWMON This driver can also be built as a module. If so, the module will be called raspberrypi-hwmon. +config SENSORS_SA67MCU + tristate "Kontron sa67mcu hardware monitoring driver" + depends on MFD_SL28CPLD || COMPILE_TEST + help + If you say yes here you get support for the voltage and temperature + monitor of the sa67 board management controller. + + This driver can also be built as a module. If so, the module + will be called sa67mcu-hwmon. + config SENSORS_SL28CPLD tristate "Kontron sl28cpld hardware monitoring driver" depends on MFD_SL28CPLD || COMPILE_TEST diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 051981eb8a50..2956898776bb 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -197,6 +197,7 @@ obj-$(CONFIG_SENSORS_PT5161L) += pt5161l.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o obj-$(CONFIG_SENSORS_QNAP_MCU_HWMON) += qnap-mcu-hwmon.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o +obj-$(CONFIG_SENSORS_SA67MCU) += sa67mcu-hwmon.o obj-$(CONFIG_SENSORS_SBTSI) += sbtsi_temp.o obj-$(CONFIG_SENSORS_SBRMI) += sbrmi.o obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o diff --git a/drivers/hwmon/sa67mcu-hwmon.c b/drivers/hwmon/sa67mcu-hwmon.c new file mode 100644 index 000000000000..22f703b7b256 --- /dev/null +++ b/drivers/hwmon/sa67mcu-hwmon.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sl67mcu hardware monitoring driver + * + * Copyright 2025 Kontron Europe GmbH + */ + +#include <linux/bitfield.h> +#include <linux/hwmon.h> +#include <linux/kernel.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/regmap.h> + +#define SA67MCU_VOLTAGE(n) (0x00 + ((n) * 2)) +#define SA67MCU_TEMP(n) (0x04 + ((n) * 2)) + +struct sa67mcu_hwmon { + struct regmap *regmap; + u32 offset; +}; + +static int sa67mcu_hwmon_read(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, long *input) +{ + struct sa67mcu_hwmon *hwmon = dev_get_drvdata(dev); + unsigned int offset; + u8 reg[2]; + int ret; + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_input: + offset = hwmon->offset + SA67MCU_VOLTAGE(channel); + break; + default: + return -EOPNOTSUPP; + } + break; + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + offset = hwmon->offset + SA67MCU_TEMP(channel); + break; + default: + return -EOPNOTSUPP; + } + break; + default: + return -EOPNOTSUPP; + } + + /* Reading the low byte will capture the value */ + ret = regmap_bulk_read(hwmon->regmap, offset, reg, ARRAY_SIZE(reg)); + if (ret) + return ret; + + *input = reg[1] << 8 | reg[0]; + + /* Temperatures are s16 and in 0.1degC steps. */ + if (type == hwmon_temp) + *input = sign_extend32(*input, 15) * 100; + + return 0; +} + +static const struct hwmon_channel_info * const sa67mcu_hwmon_info[] = { + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), + NULL +}; + +static const char *const sa67mcu_hwmon_in_labels[] = { + "VDDIN", + "VDD_RTC", +}; + +static int sa67mcu_hwmon_read_string(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, const char **str) +{ + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_label: + *str = sa67mcu_hwmon_in_labels[channel]; + return 0; + default: + return -EOPNOTSUPP; + } + default: + return -EOPNOTSUPP; + } +} + +static const struct hwmon_ops sa67mcu_hwmon_ops = { + .visible = 0444, + .read = sa67mcu_hwmon_read, + .read_string = sa67mcu_hwmon_read_string, +}; + +static const struct hwmon_chip_info sa67mcu_hwmon_chip_info = { + .ops = &sa67mcu_hwmon_ops, + .info = sa67mcu_hwmon_info, +}; + +static int sa67mcu_hwmon_probe(struct platform_device *pdev) +{ + struct sa67mcu_hwmon *hwmon; + struct device *hwmon_dev; + int ret; + + if (!pdev->dev.parent) + return -ENODEV; + + hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL); + if (!hwmon) + return -ENOMEM; + + hwmon->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!hwmon->regmap) + return -ENODEV; + + ret = device_property_read_u32(&pdev->dev, "reg", &hwmon->offset); + if (ret) + return -EINVAL; + + hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, + "sa67mcu_hwmon", hwmon, + &sa67mcu_hwmon_chip_info, + NULL); + if (IS_ERR(hwmon_dev)) + dev_err(&pdev->dev, "failed to register as hwmon device"); + + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +static const struct of_device_id sa67mcu_hwmon_of_match[] = { + { .compatible = "kontron,sa67mcu-hwmon", }, + {} +}; +MODULE_DEVICE_TABLE(of, sa67mcu_hwmon_of_match); + +static struct platform_driver sa67mcu_hwmon_driver = { + .probe = sa67mcu_hwmon_probe, + .driver = { + .name = "sa67mcu-hwmon", + .of_match_table = sa67mcu_hwmon_of_match, + }, +}; +module_platform_driver(sa67mcu_hwmon_driver); + +MODULE_DESCRIPTION("sa67mcu Hardware Monitoring Driver"); +MODULE_AUTHOR("Michael Walle <mwalle@kernel.org>"); +MODULE_LICENSE("GPL"); -- 2.39.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/7] hwmon: add SMARC-sAM67 support 2025-09-12 12:07 ` [PATCH v2 6/7] hwmon: " Michael Walle @ 2025-09-24 16:01 ` Guenter Roeck 0 siblings, 0 replies; 14+ messages in thread From: Guenter Roeck @ 2025-09-24 16:01 UTC (permalink / raw) To: Michael Walle Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean Delvare, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck, linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis On Fri, Sep 12, 2025 at 02:07:44PM +0200, Michael Walle wrote: > Add a new driver for the Kontron SMARC-sAM67 board management > controller. It has two voltage sensors and one temperature sensor. > > Signed-off-by: Michael Walle <mwalle@kernel.org> Applied. Guenter > --- > Documentation/hwmon/sa67.rst | 41 +++++++++ Note: Added to index.rst file > MAINTAINERS | 1 + > drivers/hwmon/Kconfig | 10 +++ > drivers/hwmon/Makefile | 1 + > drivers/hwmon/sa67mcu-hwmon.c | 161 ++++++++++++++++++++++++++++++++++ > 5 files changed, 214 insertions(+) > create mode 100644 Documentation/hwmon/sa67.rst > create mode 100644 drivers/hwmon/sa67mcu-hwmon.c > > diff --git a/Documentation/hwmon/sa67.rst b/Documentation/hwmon/sa67.rst > new file mode 100644 > index 000000000000..029c7c169b7f > --- /dev/null > +++ b/Documentation/hwmon/sa67.rst > @@ -0,0 +1,41 @@ > +.. SPDX-License-Identifier: GPL-2.0-only > + > +Kernel driver sa67mcu > +===================== > + > +Supported chips: > + > + * Kontron sa67mcu > + > + Prefix: 'sa67mcu' > + > + Datasheet: not available > + > +Authors: Michael Walle <mwalle@kernel.org> > + > +Description > +----------- > + > +The sa67mcu is a board management controller which also exposes a hardware > +monitoring controller. > + > +The controller has two voltage and one temperature sensor. The values are > +hold in two 8 bit registers to form one 16 bit value. Reading the lower byte > +will also capture the high byte to make the access atomic. The unit of the > +volatge sensors are 1mV and the unit of the temperature sensor is 0.1degC. > + > +Sysfs entries > +------------- > + > +The following attributes are supported. > + > +======================= ======================================================== > +in0_label "VDDIN" > +in0_input Measured VDDIN voltage. > + > +in1_label "VDD_RTC" > +in1_input Measured VDD_RTC voltage. > + > +temp1_input MCU temperature. Roughly the board temperature. > +======================= ======================================================== > + > diff --git a/MAINTAINERS b/MAINTAINERS > index fa7f80bd7b2f..69fcd5c077ae 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -23489,6 +23489,7 @@ F: Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc. > F: Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml > F: Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml > F: drivers/gpio/gpio-sl28cpld.c > +F: drivers/hwmon/sa67mcu-hwmon.c > F: drivers/hwmon/sl28cpld-hwmon.c > F: drivers/irqchip/irq-sl28cpld.c > F: drivers/pwm/pwm-sl28cpld.c > diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig > index d6769288a76e..c2f288ebdf44 100644 > --- a/drivers/hwmon/Kconfig > +++ b/drivers/hwmon/Kconfig > @@ -1905,6 +1905,16 @@ config SENSORS_RASPBERRYPI_HWMON > This driver can also be built as a module. If so, the module > will be called raspberrypi-hwmon. > > +config SENSORS_SA67MCU > + tristate "Kontron sa67mcu hardware monitoring driver" > + depends on MFD_SL28CPLD || COMPILE_TEST > + help > + If you say yes here you get support for the voltage and temperature > + monitor of the sa67 board management controller. > + > + This driver can also be built as a module. If so, the module > + will be called sa67mcu-hwmon. > + > config SENSORS_SL28CPLD > tristate "Kontron sl28cpld hardware monitoring driver" > depends on MFD_SL28CPLD || COMPILE_TEST > diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile > index 051981eb8a50..2956898776bb 100644 > --- a/drivers/hwmon/Makefile > +++ b/drivers/hwmon/Makefile > @@ -197,6 +197,7 @@ obj-$(CONFIG_SENSORS_PT5161L) += pt5161l.o > obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o > obj-$(CONFIG_SENSORS_QNAP_MCU_HWMON) += qnap-mcu-hwmon.o > obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o > +obj-$(CONFIG_SENSORS_SA67MCU) += sa67mcu-hwmon.o > obj-$(CONFIG_SENSORS_SBTSI) += sbtsi_temp.o > obj-$(CONFIG_SENSORS_SBRMI) += sbrmi.o > obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o > diff --git a/drivers/hwmon/sa67mcu-hwmon.c b/drivers/hwmon/sa67mcu-hwmon.c > new file mode 100644 > index 000000000000..22f703b7b256 > --- /dev/null > +++ b/drivers/hwmon/sa67mcu-hwmon.c > @@ -0,0 +1,161 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * sl67mcu hardware monitoring driver > + * > + * Copyright 2025 Kontron Europe GmbH > + */ > + > +#include <linux/bitfield.h> > +#include <linux/hwmon.h> > +#include <linux/kernel.h> > +#include <linux/mod_devicetable.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/property.h> > +#include <linux/regmap.h> > + > +#define SA67MCU_VOLTAGE(n) (0x00 + ((n) * 2)) > +#define SA67MCU_TEMP(n) (0x04 + ((n) * 2)) > + > +struct sa67mcu_hwmon { > + struct regmap *regmap; > + u32 offset; > +}; > + > +static int sa67mcu_hwmon_read(struct device *dev, > + enum hwmon_sensor_types type, u32 attr, > + int channel, long *input) > +{ > + struct sa67mcu_hwmon *hwmon = dev_get_drvdata(dev); > + unsigned int offset; > + u8 reg[2]; > + int ret; > + > + switch (type) { > + case hwmon_in: > + switch (attr) { > + case hwmon_in_input: > + offset = hwmon->offset + SA67MCU_VOLTAGE(channel); > + break; > + default: > + return -EOPNOTSUPP; > + } > + break; > + case hwmon_temp: > + switch (attr) { > + case hwmon_temp_input: > + offset = hwmon->offset + SA67MCU_TEMP(channel); > + break; > + default: > + return -EOPNOTSUPP; > + } > + break; > + default: > + return -EOPNOTSUPP; > + } > + > + /* Reading the low byte will capture the value */ > + ret = regmap_bulk_read(hwmon->regmap, offset, reg, ARRAY_SIZE(reg)); > + if (ret) > + return ret; > + > + *input = reg[1] << 8 | reg[0]; > + > + /* Temperatures are s16 and in 0.1degC steps. */ > + if (type == hwmon_temp) > + *input = sign_extend32(*input, 15) * 100; > + > + return 0; > +} > + > +static const struct hwmon_channel_info * const sa67mcu_hwmon_info[] = { > + HWMON_CHANNEL_INFO(in, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL), > + HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), > + NULL > +}; > + > +static const char *const sa67mcu_hwmon_in_labels[] = { > + "VDDIN", > + "VDD_RTC", > +}; > + > +static int sa67mcu_hwmon_read_string(struct device *dev, > + enum hwmon_sensor_types type, u32 attr, > + int channel, const char **str) > +{ > + switch (type) { > + case hwmon_in: > + switch (attr) { > + case hwmon_in_label: > + *str = sa67mcu_hwmon_in_labels[channel]; > + return 0; > + default: > + return -EOPNOTSUPP; > + } > + default: > + return -EOPNOTSUPP; > + } > +} > + > +static const struct hwmon_ops sa67mcu_hwmon_ops = { > + .visible = 0444, > + .read = sa67mcu_hwmon_read, > + .read_string = sa67mcu_hwmon_read_string, > +}; > + > +static const struct hwmon_chip_info sa67mcu_hwmon_chip_info = { > + .ops = &sa67mcu_hwmon_ops, > + .info = sa67mcu_hwmon_info, > +}; > + > +static int sa67mcu_hwmon_probe(struct platform_device *pdev) > +{ > + struct sa67mcu_hwmon *hwmon; > + struct device *hwmon_dev; > + int ret; > + > + if (!pdev->dev.parent) > + return -ENODEV; > + > + hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL); > + if (!hwmon) > + return -ENOMEM; > + > + hwmon->regmap = dev_get_regmap(pdev->dev.parent, NULL); > + if (!hwmon->regmap) > + return -ENODEV; > + > + ret = device_property_read_u32(&pdev->dev, "reg", &hwmon->offset); > + if (ret) > + return -EINVAL; > + > + hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, > + "sa67mcu_hwmon", hwmon, > + &sa67mcu_hwmon_chip_info, > + NULL); > + if (IS_ERR(hwmon_dev)) > + dev_err(&pdev->dev, "failed to register as hwmon device"); > + > + return PTR_ERR_OR_ZERO(hwmon_dev); > +} > + > +static const struct of_device_id sa67mcu_hwmon_of_match[] = { > + { .compatible = "kontron,sa67mcu-hwmon", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, sa67mcu_hwmon_of_match); > + > +static struct platform_driver sa67mcu_hwmon_driver = { > + .probe = sa67mcu_hwmon_probe, > + .driver = { > + .name = "sa67mcu-hwmon", > + .of_match_table = sa67mcu_hwmon_of_match, > + }, > +}; > +module_platform_driver(sa67mcu_hwmon_driver); > + > +MODULE_DESCRIPTION("sa67mcu Hardware Monitoring Driver"); > +MODULE_AUTHOR("Michael Walle <mwalle@kernel.org>"); > +MODULE_LICENSE("GPL"); ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 7/7] arm64: dts: ti: sa67: add on-board management controller node 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle ` (5 preceding siblings ...) 2025-09-12 12:07 ` [PATCH v2 6/7] hwmon: " Michael Walle @ 2025-09-12 12:07 ` Michael Walle 2025-09-25 7:28 ` [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle 7 siblings, 0 replies; 14+ messages in thread From: Michael Walle @ 2025-09-12 12:07 UTC (permalink / raw) To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michael Walle, Jean Delvare, Guenter Roeck, Lee Jones, Srinivas Kandagatla, Wim Van Sebroeck Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis Add the node for the onboard management controller which has a watchdog and hardware monitoring. Signed-off-by: Michael Walle <mwalle@kernel.org> --- .../boot/dts/ti/k3-am67a-kontron-sa67-base.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts index 5755df689752..7f05df9111ea 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -416,6 +416,24 @@ vcc_1p8_ret_s5: ldo3 { }; }; + system-controller@4a { + compatible = "kontron,sa67mcu", "kontron,sl28cpld"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + + watchdog@4 { + compatible = "kontron,sa67mcu-wdt", "kontron,sl28cpld-wdt"; + reg = <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@8 { + compatible = "kontron,sa67mcu-hwmon"; + reg = <0x8>; + }; + }; + rtc: rtc@51 { compatible = "microcrystal,rv8263"; reg = <0x51>; -- 2.39.5 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle ` (6 preceding siblings ...) 2025-09-12 12:07 ` [PATCH v2 7/7] arm64: dts: ti: sa67: add on-board management controller node Michael Walle @ 2025-09-25 7:28 ` Michael Walle 2025-09-25 11:34 ` Lee Jones 7 siblings, 1 reply; 14+ messages in thread From: Michael Walle @ 2025-09-25 7:28 UTC (permalink / raw) To: Lee Jones Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis, Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean Delvare, Guenter Roeck, Michael Walle, Srinivas Kandagatla, Wim Van Sebroeck [-- Attachment #1: Type: text/plain, Size: 1818 bytes --] Hi Lee, On Fri Sep 12, 2025 at 2:07 PM CEST, Michael Walle wrote: > Now that the PMIC support is there, we can finally, upstream the > support for this board. Besides the usual device tree, this > patchset contains the support for the on-board house keeping MCU. It > make extensive reuse of the drivers for the former SMARC-sAL28 > board. Besides different hwmon sensors, all the dt binding patches > will just add a board specific compatible (in addition to the old > sl28 compatible) to make any future board specific quirks possible. > > I'm aware that there is a patch [1] which moves the sl28cpld MFD > schema to a different directory. Once that patch is merged, I'll > repost this series. But I already want to get some early feedback. > > v2: > - dropped patches which were already picked up > - new patch "dt-bindings: mfd: tps6594: allow gpio-line-names" > - separate driver for the hwmon, add missing hwmon documentation, > thanks Guenter > - split the DT as suggested by the SoC maintainers > - add missing copyright and license to the overlays, thanks Andrew > > Michael Walle (7): > dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module > dt-bindings: mfd: tps6594: allow gpio-line-names > arm64: dts: ti: Add support for Kontron SMARC-sAM67 > dt-bindings: hwmon: sl28cpld: add sa67mcu compatible > dt-bindings: watchdog: add SMARC-sAM67 support > hwmon: add SMARC-sAM67 support > arm64: dts: ti: sa67: add on-board management controller node Would you take these two patches dt-bindings: mfd: tps6594: allow gpio-line-names dt-bindings: watchdog: add SMARC-sAM67 support through the MFD tree this cycle? If they make it in, there wouldn't be any more dependencies for the next cycle for the actual device tree. Thanks, -michael [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 297 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support 2025-09-25 7:28 ` [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle @ 2025-09-25 11:34 ` Lee Jones 0 siblings, 0 replies; 14+ messages in thread From: Lee Jones @ 2025-09-25 11:34 UTC (permalink / raw) To: Michael Walle Cc: linux-arm-kernel, devicetree, linux-kernel, linux-hwmon, linux-watchdog, Andrew Davis, Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean Delvare, Guenter Roeck, Srinivas Kandagatla, Wim Van Sebroeck On Thu, 25 Sep 2025, Michael Walle wrote: > Hi Lee, > > On Fri Sep 12, 2025 at 2:07 PM CEST, Michael Walle wrote: > > Now that the PMIC support is there, we can finally, upstream the > > support for this board. Besides the usual device tree, this > > patchset contains the support for the on-board house keeping MCU. It > > make extensive reuse of the drivers for the former SMARC-sAL28 > > board. Besides different hwmon sensors, all the dt binding patches > > will just add a board specific compatible (in addition to the old > > sl28 compatible) to make any future board specific quirks possible. > > > > I'm aware that there is a patch [1] which moves the sl28cpld MFD > > schema to a different directory. Once that patch is merged, I'll > > repost this series. But I already want to get some early feedback. > > > > v2: > > - dropped patches which were already picked up > > - new patch "dt-bindings: mfd: tps6594: allow gpio-line-names" > > - separate driver for the hwmon, add missing hwmon documentation, > > thanks Guenter > > - split the DT as suggested by the SoC maintainers > > - add missing copyright and license to the overlays, thanks Andrew > > > > Michael Walle (7): > > dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module > > dt-bindings: mfd: tps6594: allow gpio-line-names > > arm64: dts: ti: Add support for Kontron SMARC-sAM67 > > dt-bindings: hwmon: sl28cpld: add sa67mcu compatible > > dt-bindings: watchdog: add SMARC-sAM67 support > > hwmon: add SMARC-sAM67 support > > arm64: dts: ti: sa67: add on-board management controller node > > Would you take these two patches > dt-bindings: mfd: tps6594: allow gpio-line-names > dt-bindings: watchdog: add SMARC-sAM67 support > > through the MFD tree this cycle? If they make it in, there wouldn't > be any more dependencies for the next cycle for the actual device > tree. Applied both, thanks. -- Lee Jones [李琼斯] ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-09-25 11:34 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-09-12 12:07 [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle 2025-09-12 12:07 ` [PATCH v2 1/7] dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module Michael Walle 2025-09-12 12:07 ` [PATCH v2 2/7] dt-bindings: mfd: tps6594: allow gpio-line-names Michael Walle 2025-09-15 21:34 ` Rob Herring (Arm) 2025-09-12 12:07 ` [PATCH v2 3/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67 Michael Walle 2025-09-12 12:07 ` [PATCH v2 4/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible Michael Walle 2025-09-24 16:00 ` Guenter Roeck 2025-09-12 12:07 ` [PATCH v2 5/7] dt-bindings: watchdog: add SMARC-sAM67 support Michael Walle 2025-09-24 15:59 ` Guenter Roeck 2025-09-12 12:07 ` [PATCH v2 6/7] hwmon: " Michael Walle 2025-09-24 16:01 ` Guenter Roeck 2025-09-12 12:07 ` [PATCH v2 7/7] arm64: dts: ti: sa67: add on-board management controller node Michael Walle 2025-09-25 7:28 ` [PATCH v2 0/7] Initial Kontron SMARC-sAM67 support Michael Walle 2025-09-25 11:34 ` Lee Jones
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