From: sathyanarayanan kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Andy Shevchenko <andy@infradead.org>,
Zha Qipeng <qipeng.zha@intel.com>,
"dvhart@infradead.org" <dvhart@infradead.org>,
Guenter Roeck <linux@roeck-us.net>,
Wim Van Sebroeck <wim@iguana.be>,
Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com>,
David Box <david.e.box@linux.intel.com>,
Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>,
Platform Driver <platform-driver-x86@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-watchdog@vger.kernel.org
Subject: Re: [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset
Date: Tue, 25 Apr 2017 10:34:43 -0700 [thread overview]
Message-ID: <c1a6ee3d-ded0-fc6d-3f3e-d7f8b4c2e323@linux.intel.com> (raw)
In-Reply-To: <CAHp75VcZAtpVDW2BbHZ5-3NZX4tgmz24U4=-oYTq-_h+eUTdFw@mail.gmail.com>
On 04/25/2017 06:29 AM, Andy Shevchenko wrote:
> On Mon, Apr 10, 2017 at 1:00 AM, Kuppuswamy Sathyanarayanan
> <sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
>> According to Broxton APL spec, PMC MIMO resources for Global Control
>> Registers(GCR) are located at 4K(0x1000) offset from IPC base address.
>> In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR
>> region base address from IPC base address and its current value of
>> 0x1008 is incorrect because it points to location for PMC_CFG register
>> and not the GCR base address itself.
>>
>> GCR Base = IPC1 Base + 0x1000.
>>
>> This patch fixes this offset issue.
> The whole series has been pushed to testing, thanks.
Thanks Andy.
>
>> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>> ---
>> drivers/platform/x86/intel_pmc_ipc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> Changes since v6:
>> * Updated commit message
>>
>> Changes since v5:
>> * None
>>
>> Changes since v4:
>> * None
>>
>> Changes since v3:
>> * Updated the commit history
>>
>> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c
>> index 0651d47..0a33592 100644
>> --- a/drivers/platform/x86/intel_pmc_ipc.c
>> +++ b/drivers/platform/x86/intel_pmc_ipc.c
>> @@ -82,7 +82,7 @@
>> /* exported resources from IFWI */
>> #define PLAT_RESOURCE_IPC_INDEX 0
>> #define PLAT_RESOURCE_IPC_SIZE 0x1000
>> -#define PLAT_RESOURCE_GCR_OFFSET 0x1008
>> +#define PLAT_RESOURCE_GCR_OFFSET 0x1000
>> #define PLAT_RESOURCE_GCR_SIZE 0x1000
>> #define PLAT_RESOURCE_BIOS_DATA_INDEX 1
>> #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
>> --
>> 2.7.4
>>
>
>
--
Sathyanarayanan Kuppuswamy
Android kernel developer
prev parent reply other threads:[~2017-04-25 17:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-09 22:00 [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset Kuppuswamy Sathyanarayanan
2017-04-09 22:00 ` [PATCH v7 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan
2017-04-09 22:00 ` [PATCH v7 3/6] watchdog: iTCO_wdt: cleanup set/unset no_reboot_bit functions Kuppuswamy Sathyanarayanan
2017-04-10 12:51 ` Guenter Roeck
2017-04-10 12:51 ` Guenter Roeck
2017-04-09 22:00 ` [PATCH v7 4/6] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan
2017-04-09 22:00 ` [PATCH v7 5/6] platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure Kuppuswamy Sathyanarayanan
2017-04-09 22:00 ` [PATCH v7 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan
2017-04-25 13:29 ` [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset Andy Shevchenko
2017-04-25 17:34 ` sathyanarayanan kuppuswamy [this message]
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