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From: Krzysztof Kozlowski <krzk@kernel.org>
To: CL Wang <cl634@andestech.com>,
	wim@linux-watchdog.org, linux@roeck-us.net, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-watchdog@vger.kernel.org, tim609@andestech.com
Subject: Re: [PATCH 2/3] watchdog: atcwdt200: Add driver for Andes ATCWDT200
Date: Wed, 7 Jan 2026 16:46:18 +0100	[thread overview]
Message-ID: <f6499c9a-4ec8-4c9e-b9b5-e679e0f913a4@kernel.org> (raw)
In-Reply-To: <20260107145058.213334-3-cl634@andestech.com>

On 07/01/2026 15:50, CL Wang wrote:
> +
> +static int atcwdt_enable_clk(struct atcwdt_drv *drv_data)
> +{
> +	struct device *dev = drv_data->wdt_dev.parent;
> +	unsigned int val;
> +	int ret;
> +
> +	drv_data->clk = devm_clk_get(dev, NULL);

Just use API for getting enabled clock.

> +	if (IS_ERR(drv_data->clk))
> +		return dev_err_probe(dev, PTR_ERR(drv_data->clk),
> +				     "Failed to get watchdog clock\n");
> +
> +	ret = clk_prepare_enable(drv_data->clk);
> +	if (ret)
> +		return dev_err_probe(dev, ret,
> +				     "Failed to enable clock\n");
> +
> +	drv_data->clk_freq = clk_get_rate(drv_data->clk);
> +	if (!drv_data->clk_freq)
> +		return dev_err_probe(dev, -EINVAL,
> +				     "Failed to get clock rate\n");
> +
> +	ret = device_property_read_u32(dev, "andestech,clock-source", &val);

No, read your binding. You said it is a list... list of phandles?

> +	drv_data->clk_src = (!ret && val != 0) ? CTRL_CLK_SEL_PCLK : 0;
> +
> +	return 0;
> +}
> +
> +static int atcwdt_init_wdt_device(struct device *dev,
> +				  struct atcwdt_drv *drv_data)
> +{
> +	struct watchdog_device *wdd = &drv_data->wdt_dev;
> +
> +	wdd->parent = dev;
> +	wdd->info = &atcwdt_info;
> +	wdd->ops = &atcwdt_ops;
> +	wdd->timeout = ATCWDT_TIMEOUT;
> +	wdd->min_timeout = 1;
> +
> +	watchdog_set_nowayout(wdd, nowayout);
> +	watchdog_set_drvdata(wdd, drv_data);
> +
> +	return 0;
> +}
> +
> +static void atcwdt_calc_max_timeout(struct atcwdt_drv *drv_data)
> +{
> +	unsigned char rst_idx = atcwdt_get_index(0xFF, TMR_RST);
> +	unsigned char int_idx = atcwdt_get_index(0xFF,
> +						 drv_data->int_timer_type);
> +
> +	drv_data->wdt_dev.max_timeout =
> +		((1U << rst_idx) + (1U << int_idx)) / drv_data->clk_freq;
> +}
> +
> +static int atcwdt_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct atcwdt_drv *drv_data;
> +	int ret;
> +
> +	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
> +	if (!drv_data)
> +		return -ENOMEM;
> +
> +	platform_set_drvdata(pdev, drv_data);
> +	spin_lock_init(&drv_data->lock);
> +
> +	ret = atcwdt_init_wdt_device(dev, drv_data);
> +	if (ret)
> +		return ret;
> +
> +	ret = atcwdt_init_resource(pdev, drv_data);
> +	if (ret)
> +		return ret;
> +
> +	ret = atcwdt_enable_clk(drv_data);
> +	if (ret)
> +		return ret;
> +
> +	ret = atcwdt_get_int_timer_type(drv_data);
> +	if (ret)
> +		goto disable_clk;
> +
> +	atcwdt_calc_max_timeout(drv_data);
> +
> +	ret = devm_watchdog_register_device(dev, &drv_data->wdt_dev);
> +	if (ret)
> +		goto disable_clk;
> +
> +	return 0;
> +
> +disable_clk:
> +	clk_disable_unprepare(drv_data->clk);
> +
> +	return ret;
> +}
> +
> +static int atcwdt_suspend(struct device *dev)
> +{
> +	struct atcwdt_drv *drv_data = dev_get_drvdata(dev);
> +
> +	if (watchdog_active(&drv_data->wdt_dev)) {
> +		atcwdt_stop(&drv_data->wdt_dev);
> +		clk_disable_unprepare(drv_data->clk);
> +	}
> +
> +	return 0;
> +}
> +
> +static int atcwdt_resume(struct device *dev)
> +{
> +	struct atcwdt_drv *drv_data = dev_get_drvdata(dev);
> +	int ret = 0;
> +
> +	if (watchdog_active(&drv_data->wdt_dev)) {
> +		ret = clk_prepare_enable(drv_data->clk);
> +		if (ret)
> +			goto clk_prepare_err;

Just return.

> +
> +		atcwdt_start(&drv_data->wdt_dev);
> +		atcwdt_ping(&drv_data->wdt_dev);
> +	}
> +
> +clk_prepare_err:
> +	return ret;
> +}
> +
> +static const struct of_device_id atcwdt_match[] = {
> +	{ .compatible = "andestech,qilai-wdt" },

Drop, not needed.

> +	{ .compatible = "andestech,ae350-wdt" },
> +	{ /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, atcwdt_match);
> +
> +static DEFINE_SIMPLE_DEV_PM_OPS(atcwdt_pm_ops, atcwdt_suspend, atcwdt_resume);
> +
> +static struct platform_driver atcwdt_driver = {
> +	.probe		= atcwdt_probe,
> +	.driver		= {
> +		.name	= DRV_NAME,
> +		.owner	= THIS_MODULE,

From where did you get this?

> +		.of_match_table = atcwdt_match,
> +		.pm = pm_sleep_ptr(&atcwdt_pm_ops),
> +	},
> +};
> +
> +module_platform_driver(atcwdt_driver);
> +
> +module_param(timeout, uint, 0);
> +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
> +		 __MODULE_STRING(ATCWDT_TIMEOUT) ")");
> +
> +module_param(nowayout, bool, 0);
> +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
> +		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("CL Wang <cl634@andestech.com>");
> +MODULE_DESCRIPTION("Andes ATCWDT200 Watchdog timer driver");


Best regards,
Krzysztof

  reply	other threads:[~2026-01-07 15:46 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-07 14:50 [PATCH 0/3] watchdog: Add support for Andes ATCWDT200 CL Wang
2026-01-07 14:50 ` [PATCH 1/3] dt-bindings: " CL Wang
2026-01-07 15:44   ` Krzysztof Kozlowski
2026-01-09  9:35     ` CL Wang
2026-01-07 16:23   ` Rob Herring (Arm)
2026-01-12  6:59     ` CL Wang
2026-01-07 14:50 ` [PATCH 2/3] watchdog: atcwdt200: Add driver " CL Wang
2026-01-07 15:46   ` Krzysztof Kozlowski [this message]
2026-01-12  7:05     ` CL Wang
2026-01-07 14:50 ` [PATCH 3/3] MAINTAINERS: Add entry " CL Wang

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