From: Vasanthakumar Thiagarajan <vasanth@atheros.com>
To: <linville@tuxdriver.com>
Cc: <linux-wireless@vger.kernel.org>
Subject: [PATCH 03/22] ath9k_hw: Introduce a bool for 25mhz clock and populate it
Date: Tue, 12 Apr 2011 18:47:41 +0530 [thread overview]
Message-ID: <1302614273-2063-1-git-send-email-vasanth@atheros.com> (raw)
pll configuration will differ for 25mhz clock.
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
---
drivers/net/wireless/ath/ath9k/hw.c | 11 +++++++++++
drivers/net/wireless/ath/ath9k/hw.h | 2 ++
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index d98b4c6..8b90b9c 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -481,6 +481,9 @@ static void ath9k_hw_attach_ops(struct ath_hw *ah)
/* Called for all hardware families */
static int __ath9k_hw_init(struct ath_hw *ah)
{
+#define AR9340_SOC_SEL_25M_40M 0xB80600B0
+#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */
+
struct ath_common *common = ath9k_hw_common(ah);
int r = 0;
@@ -508,6 +511,14 @@ static int __ath9k_hw_init(struct ath_hw *ah)
ath9k_hw_attach_ops(ah);
+ if (AR_SREV_9340(ah)) {
+ if (*((volatile u32 *) AR9340_SOC_SEL_25M_40M) &
+ AR9340_REF_CLK_40)
+ ah->is_clk_25mhz = false;
+ else
+ ah->is_clk_25mhz = true;
+ }
+
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
ath_err(common, "Couldn't wakeup chip\n");
return -EIO;
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index afdb006..721eb27 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -845,6 +845,8 @@ struct ath_hw {
/* Enterprise mode cap */
u32 ent_mode;
+
+ bool is_clk_25mhz;
};
static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
--
1.7.0.4
next reply other threads:[~2011-04-12 13:17 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-12 13:17 Vasanthakumar Thiagarajan [this message]
2011-04-12 13:17 ` [PATCH 04/22] ath9k_hw: Configure pll control register accordingly for AR9340 Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 06/22] ath9k_hw: Initialize mode registers from initvals.h " Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 07/22] ath9k_hw: Don't do ani initialization " Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 09/22] ath9k_hw: Read spur frequency information from eeprom " Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 10/22] ath9k_hw: Configure RF channel freqency " Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 11/22] ath9k_hw: Clean up rx/tx chain configuration before AGC/IQ cal Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 14/22] ath9k_hw: Skip internal regulator configuration for AR9340 Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 15/22] ath9k_hw: Configure tuning capacitance value for AR9340 as well Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 17/22] ath9k_hw: Configure chain switch table and attenuation control only for active chains Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 18/22] ath9k_hw: Read iq calibration data " Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 21/22] ath9k_hw: Disable INTR_HOST1_FATAL to avoid interrupt strom with ar9430 Vasanthakumar Thiagarajan
2011-04-12 13:17 ` [PATCH 22/22] ath9k_hw: Enable AR9340 support Vasanthakumar Thiagarajan
2011-04-12 13:50 ` [PATCH 03/22] ath9k_hw: Introduce a bool for 25mhz clock and populate it Felix Fietkau
2011-04-12 14:00 ` Vasanthakumar Thiagarajan
2011-04-12 14:33 ` Vasanthakumar Thiagarajan
2011-04-12 14:51 ` John W. Linville
2011-04-19 5:49 ` Vasanthakumar Thiagarajan
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