* [PATCH 1/2] ath9k: Add initval arrays for DFS channels
@ 2013-12-04 4:29 Sujith Manoharan
2013-12-04 4:29 ` [PATCH 2/2] ath9k: Initialize baseband " Sujith Manoharan
2013-12-04 7:41 ` [PATCH 1/2] ath9k: Add initval arrays " Sujith Manoharan
0 siblings, 2 replies; 3+ messages in thread
From: Sujith Manoharan @ 2013-12-04 4:29 UTC (permalink / raw)
To: John Linville; +Cc: linux-wireless
From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
---
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h | 7 +++++++
drivers/net/wireless/ath/ath9k/ar9340_initvals.h | 2 ++
drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h | 13 +++++++++++--
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index e7cdf11..97b4bd1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -1745,4 +1745,11 @@ static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
{0x0000a3a0, 0xca9228ee},
};
+static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {
+ /* Addr 5G 2G */
+ {0x00009824, 0x5ac668d0, 0x5ac668d0},
+ {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
+ {0x00009e14, 0x37b9625e, 0x37b9625e},
+};
+
#endif /* INITVALS_9003_2P2_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
index 7f22cb2..a01f0ed 100644
--- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
@@ -30,6 +30,8 @@
#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
+#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
+
static const u32 ar9340_1p0_radio_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
diff --git a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
index 75bef11..e6aec2c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
@@ -57,8 +57,6 @@ static const u32 ar9580_1p0_baseband_core[][2] = {
{0x00009804, 0xfd14e000},
{0x00009808, 0x9c0a9f6b},
{0x0000980c, 0x04900000},
- {0x00009814, 0x3280c00a},
- {0x00009818, 0x00000000},
{0x0000981c, 0x00020028},
{0x00009834, 0x6400a190},
{0x00009838, 0x0108ecff},
@@ -1133,6 +1131,8 @@ static const u32 ar9580_1p0_rx_gain_table[][2] = {
static const u32 ar9580_1p0_baseband_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
+ {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a},
+ {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
{0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
{0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
@@ -1207,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll_on_clkreq[][2] = {
{0x00004044, 0x00000000},
};
+static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = {
+ /* Addr 5G 2G */
+ {0x00009814, 0x3400c00f, 0x3400c00f},
+ {0x00009824, 0x5ac668d0, 0x5ac668d0},
+ {0x00009828, 0x06903080, 0x06903080},
+ {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
+ {0x00009e14, 0x37b9625e, 0x37b9625e},
+};
+
#endif /* INITVALS_9580_1P0_H */
--
1.8.4.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] ath9k: Initialize baseband for DFS channels
2013-12-04 4:29 [PATCH 1/2] ath9k: Add initval arrays for DFS channels Sujith Manoharan
@ 2013-12-04 4:29 ` Sujith Manoharan
2013-12-04 7:41 ` [PATCH 1/2] ath9k: Add initval arrays " Sujith Manoharan
1 sibling, 0 replies; 3+ messages in thread
From: Sujith Manoharan @ 2013-12-04 4:29 UTC (permalink / raw)
To: John Linville; +Cc: linux-wireless
From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Certain baseband registers require different values
to be programmed when operating in a DFS channel to
ensure that radar detection works correctly. This
is required for AR9300, AR9340 and AR9580.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
---
drivers/net/wireless/ath/ath9k/ar9003_hw.c | 6 ++++++
drivers/net/wireless/ath/ath9k/ar9003_phy.c | 6 ++++++
drivers/net/wireless/ath/ath9k/hw.h | 1 +
3 files changed, 13 insertions(+)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index d8c1eee..4e8ae4a 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -152,6 +152,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9340Modes_fast_clock_1p0);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
+ INIT_INI_ARRAY(&ah->ini_dfs,
+ ar9340_1p0_baseband_postamble_dfs_channel);
if (!ah->is_clk_25mhz)
INIT_INI_ARRAY(&ah->iniAdditional,
@@ -340,6 +342,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9580_1p0_modes_fast_clock);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
+ INIT_INI_ARRAY(&ah->ini_dfs,
+ ar9580_1p0_baseband_postamble_dfs_channel);
} else if (AR_SREV_9565_11_OR_LATER(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
ar9565_1p1_mac_core);
@@ -458,6 +462,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9300Modes_fast_clock_2p2);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
+ INIT_INI_ARRAY(&ah->ini_dfs,
+ ar9300_2p2_baseband_postamble_dfs_channel);
}
}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 39b71b3..9f051a0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1332,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
static void ar9003_hw_set_radar_params(struct ath_hw *ah,
struct ath_hw_radar_conf *conf)
{
+ unsigned int regWrites = 0;
u32 radar_0 = 0, radar_1 = 0;
if (!conf) {
@@ -1358,6 +1359,11 @@ static void ar9003_hw_set_radar_params(struct ath_hw *ah,
REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
else
REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+
+ if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
+ REG_WRITE_ARRAY(&ah->ini_dfs,
+ IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
+ }
}
static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index e508436..7490047 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -864,6 +864,7 @@ struct ath_hw {
u32 gpio_mask;
u32 gpio_val;
+ struct ar5416IniArray ini_dfs;
struct ar5416IniArray iniModes;
struct ar5416IniArray iniCommon;
struct ar5416IniArray iniBB_RfGain;
--
1.8.4.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] ath9k: Add initval arrays for DFS channels
2013-12-04 4:29 [PATCH 1/2] ath9k: Add initval arrays for DFS channels Sujith Manoharan
2013-12-04 4:29 ` [PATCH 2/2] ath9k: Initialize baseband " Sujith Manoharan
@ 2013-12-04 7:41 ` Sujith Manoharan
1 sibling, 0 replies; 3+ messages in thread
From: Sujith Manoharan @ 2013-12-04 7:41 UTC (permalink / raw)
To: John Linville; +Cc: linux-wireless
Hi,
I'll squash these two patches into another series that also adds
updates for AR9331.
Sujith
Sujith Manoharan wrote:
> From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
>
> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
> ---
> drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h | 7 +++++++
> drivers/net/wireless/ath/ath9k/ar9340_initvals.h | 2 ++
> drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h | 13 +++++++++++--
> 3 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
> index e7cdf11..97b4bd1 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
> +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
> @@ -1745,4 +1745,11 @@ static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
> {0x0000a3a0, 0xca9228ee},
> };
>
> +static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {
> + /* Addr 5G 2G */
> + {0x00009824, 0x5ac668d0, 0x5ac668d0},
> + {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
> + {0x00009e14, 0x37b9625e, 0x37b9625e},
> +};
> +
> #endif /* INITVALS_9003_2P2_H */
> diff --git a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
> index 7f22cb2..a01f0ed 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
> +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
> @@ -30,6 +30,8 @@
>
> #define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
>
> +#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
> +
> static const u32 ar9340_1p0_radio_postamble[][5] = {
> /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
> {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
> diff --git a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
> index 75bef11..e6aec2c 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
> +++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
> @@ -57,8 +57,6 @@ static const u32 ar9580_1p0_baseband_core[][2] = {
> {0x00009804, 0xfd14e000},
> {0x00009808, 0x9c0a9f6b},
> {0x0000980c, 0x04900000},
> - {0x00009814, 0x3280c00a},
> - {0x00009818, 0x00000000},
> {0x0000981c, 0x00020028},
> {0x00009834, 0x6400a190},
> {0x00009838, 0x0108ecff},
> @@ -1133,6 +1131,8 @@ static const u32 ar9580_1p0_rx_gain_table[][2] = {
> static const u32 ar9580_1p0_baseband_postamble[][5] = {
> /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
> {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
> + {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a},
> + {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
> {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
> {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
> {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
> @@ -1207,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll_on_clkreq[][2] = {
> {0x00004044, 0x00000000},
> };
>
> +static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = {
> + /* Addr 5G 2G */
> + {0x00009814, 0x3400c00f, 0x3400c00f},
> + {0x00009824, 0x5ac668d0, 0x5ac668d0},
> + {0x00009828, 0x06903080, 0x06903080},
> + {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
> + {0x00009e14, 0x37b9625e, 0x37b9625e},
> +};
> +
> #endif /* INITVALS_9580_1P0_H */
> --
> 1.8.4.2
>
> --
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^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2013-12-04 7:45 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2013-12-04 4:29 [PATCH 1/2] ath9k: Add initval arrays for DFS channels Sujith Manoharan
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