From: Johannes Berg <johannes@sipsolutions.net>
To: Peter Oh <poh@qca.qualcomm.com>
Cc: Bob Copeland <me@bobcopeland.com>,
ath10k@lists.infradead.org, linux-wireless@vger.kernel.org
Subject: Re: [PATCH] ath10k: Replace ioread with wmb for data sync
Date: Wed, 28 Jan 2015 08:37:23 +0100 [thread overview]
Message-ID: <1422430643.1973.1.camel@sipsolutions.net> (raw)
In-Reply-To: <54C875FD.3070101@qca.qualcomm.com> (sfid-20150128_064104_435635_7E681844)
On Tue, 2015-01-27 at 21:39 -0800, Peter Oh wrote:
> > Ok, sure, but I/O ordering two different writes, and ensuring device
> > has seen a posted write, are related but different things, no?
> yes, they are different and wmb guarantees both.
No, wmb() doesn't. I'd be very surprised if it had any side effect on
the PCI bus even on ARM. Read Documentation/memory-barriers.txt.
And to understand (PCI) posted writes, wikipedia helps:
http://en.wikipedia.org/wiki/Posted_write
johannes
next prev parent reply other threads:[~2015-01-28 20:18 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-26 22:25 [PATCH] ath10k: Replace ioread with wmb for data sync Peter Oh
2015-01-27 21:33 ` Bob Copeland
2015-01-27 23:53 ` Peter Oh
2015-01-28 4:30 ` Bob Copeland
2015-01-28 5:39 ` Peter Oh
2015-01-28 7:37 ` Johannes Berg [this message]
2015-01-30 22:53 ` Peter Oh
2015-01-31 1:16 ` Sujith Manoharan
2015-01-31 1:56 ` Peter Oh
2015-01-31 2:06 ` Sujith Manoharan
2015-02-02 17:25 ` Peter Oh
2015-02-02 22:26 ` Adrian Chadd
2015-02-02 23:04 ` Peter Oh
2015-02-02 13:02 ` Johannes Berg
2015-02-02 17:33 ` Peter Oh
2015-02-02 18:54 ` Johannes Berg
2015-02-02 19:15 ` Peter Oh
2015-02-02 19:22 ` Johannes Berg
2015-02-02 19:36 ` Peter Oh
2015-02-02 19:47 ` Johannes Berg
2015-02-02 22:06 ` Peter Oh
2015-02-02 23:25 ` Florian Fainelli
2015-02-02 23:49 ` Peter Oh
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