[patch 1/5] ssb: pcicore compile fix

[patch 1/5] ssb: pcicore compile fix

[Michael Buesch]

From: Aurelien Jarno <aurelien@aurel32.net>

The patch below against 2.6.23-rc1-mm1 fixes the definition of
pcibios_map_irq in the SSB code. The corresponding include file has been
changed in commit 19df0d1169b3ddcc84933794d1401aaafe2f0000.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Michael Buesch <mb@bu3sch.de>

Index: ssb-merge/drivers/ssb/driver_pcicore.c
===================================================================
--- ssb-merge.orig/drivers/ssb/driver_pcicore.c	2007-08-10 13:30:22.000000000 +0200
+++ ssb-merge/drivers/ssb/driver_pcicore.c	2007-08-10 13:30:23.000000000 +0200
@@ -102,7 +102,7 @@ static void __init ssb_fixup_pcibridge(s
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
 
-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 	return ssb_mips_irq(extpci_core->dev) + 2;
 }

-- 

[patch 2/5] ssb: pci core driver fixes

[Michael Buesch]

From: Aurelien Jarno <aurelien@aurel32.net>

Fixes various things on the SSB
PCI core driver:
 - Correctly write the configuration register value in 
   ssb_extpci_write_config() for len = 1 or len = 2.
 - Set the PCI_LATENCY_TIMER to handle devices on the PCI bus.
 - Set the PCI arbiter control to internal.
 - Add some delay between the configuration of the PCI controller 
   and its registration.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Michael Buesch <mb@bu3sch.de>

Index: ssb-merge/drivers/ssb/driver_pcicore.c
===================================================================
--- ssb-merge.orig/drivers/ssb/driver_pcicore.c	2007-08-10 13:30:23.000000000 +0200
+++ ssb-merge/drivers/ssb/driver_pcicore.c	2007-08-10 13:30:50.000000000 +0200
@@ -99,6 +99,9 @@ static void __init ssb_fixup_pcibridge(s
 
 	/* Enable PCI bridge BAR1 prefetch and burst */
 	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
+
+	/* Make sure our latency is high enough to handle the devices behind us */
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
 
@@ -230,7 +233,7 @@ static int ssb_extpci_write_config(struc
 		val = *((const u32 *)buf);
 		break;
 	}
-	writel(*((const u32 *)buf), mmio);
+	writel(val, mmio);
 
 	err = 0;
 unmap:
@@ -311,6 +314,8 @@ static void ssb_pcicore_init_hostmode(st
 	udelay(150); /* Assertion time demanded by the PCI standard */
 	val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
 	pcicore_write32(pc, SSB_PCICORE_CTL, val);
+	val = SSB_PCICORE_ARBCTL_INTERN;
+	pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
 	udelay(1); /* Assertion time demanded by the PCI standard */
 
 	/*TODO cardbus mode */
@@ -340,6 +345,9 @@ static void ssb_pcicore_init_hostmode(st
 	 * The following needs change, if we want to port hostmode
 	 * to non-MIPS platform. */
 	set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
+	/* Give some time to the PCI controller to configure itself with the new
+	 * values. Not waiting at this point causes crashes of the machine. */
+	mdelay(10);
 	register_pci_controller(&ssb_pcicore_controller);
 }
 

-- 

[patch 3/5] ssb: Read the UART divisor instead of setting it

[Michael Buesch]

From: Aurelien Jarno <aurelien@aurel32.net>

I finally have one more patch for the SSB bus driver. I have ported the
BCM947xx code to the CFE API that is already in the kernel, and I have
seen that when the chip common driver initializes the serial port, it
breaks the CFE console (used as an early console until the serial port
is initialized). This is due to the change of the UART clock in 
ssb_chipco_serial_init().

The patch below reads the current UART divisor value and use it to 
compute baud_base instead of forcing a fixed divisor value. This limits
the maximum speed of the serial port, but don't forget the SSB bus runs 
at around 100MHz. CFE initializes the divisor so that baud_base equals 
1.8432MHz, which is already fast for a serial port.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Index: ssb-merge/drivers/ssb/driver_chipcommon.c
===================================================================
--- ssb-merge.orig/drivers/ssb/driver_chipcommon.c	2007-08-10 13:30:21.000000000 +0200
+++ ssb-merge/drivers/ssb/driver_chipcommon.c	2007-08-10 13:31:14.000000000 +0200
@@ -375,10 +375,8 @@ int ssb_chipco_serial_init(struct ssb_ch
 		} else if (cc->dev->id.revision >= 3) {
 			/* Internal backplane clock */
 			baud_base = ssb_clockspeed(bus);
-			div = 2; /* Minimum divisor */
-			chipco_write32(cc, SSB_CHIPCO_CLKDIV,
-				       (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
-					& ~SSB_CHIPCO_CLKDIV_UART) | div);
+			div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
+			      & SSB_CHIPCO_CLKDIV_UART;
 		} else {
 			/* Fixed internal backplane clock */
 			baud_base = 88000000;

-- 

[patch 4/5] ssb: Fix EXPERIMENTAL annotations

[Michael Buesch]

ssb-core is not experimental anymore.

Signed-off-by: Michael Buesch <mb@bu3sch.de>

Index: ssb-merge/drivers/ssb/Kconfig
===================================================================
--- ssb-merge.orig/drivers/ssb/Kconfig	2007-08-10 12:52:50.000000000 +0200
+++ ssb-merge/drivers/ssb/Kconfig	2007-08-10 13:35:27.000000000 +0200
@@ -2,7 +2,7 @@ menu "Sonics Silicon Backplane"
 
 config SSB
 	tristate "Sonics Silicon Backplane support"
-	depends on EXPERIMENTAL && HAS_IOMEM
+	depends on HAS_IOMEM
 	help
 	  Support for the Sonics Silicon Backplane bus
 
@@ -21,8 +21,8 @@ config SSB_PCIHOST
 	  If unsure, say Y
 
 config SSB_PCMCIAHOST
-	bool "Support for SSB on PCMCIA-bus host"
-	depends on SSB && PCMCIA
+	bool "Support for SSB on PCMCIA-bus host (EXPERIMENTAL)"
+	depends on SSB && PCMCIA && EXPERIMENTAL
 	help
 	  Support for a Sonics Silicon Backplane on top
 	  of a PCMCIA device.
@@ -65,14 +65,14 @@ config SSB_DRIVER_PCICORE
 	  If unsure, say Y
 
 config SSB_PCICORE_HOSTMODE
-	bool "Hostmode support for SSB PCI core"
-	depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS
+	bool "Hostmode support for SSB PCI core (EXPERIMENTAL)"
+	depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS && EXPERIMENTAL
 	help
 	  PCIcore hostmode operation (external PCI bus).
 
 config SSB_DRIVER_MIPS
-	bool "SSB Broadcom MIPS core driver"
-	depends on SSB && MIPS
+	bool "SSB Broadcom MIPS core driver (EXPERIMENTAL)"
+	depends on SSB && MIPS && EXPERIMENTAL
 	select SSB_SERIAL
 	help
 	  Driver for the Sonics Silicon Backplane attached
@@ -81,8 +81,8 @@ config SSB_DRIVER_MIPS
 	  If unsure, say N
 
 config SSB_DRIVER_EXTIF
-	bool "SSB Broadcom EXTIF core driver"
-	depends on SSB_DRIVER_MIPS
+	bool "SSB Broadcom EXTIF core driver (EXPERIMENTAL)"
+	depends on SSB_DRIVER_MIPS && EXPERIMENTAL
 	help
 	  Driver for the Sonics Silicon Backplane attached
 	  Broadcom EXTIF core.

-- 

[patch 5/5] ssb: Remove verbose coreswitch printk

[Michael Buesch]

This makes the verbose printk on every coreswitch dependent
on a default-off debugging variable.
Verbose coreswitch messages are only needed when debugging
strange crashes or machine check exceptions.

Signed-off-by: Michael Buesch <mb@bu3sch.de>

Index: ssb-merge/drivers/ssb/pci.c
===================================================================
--- ssb-merge.orig/drivers/ssb/pci.c	2007-08-10 12:52:50.000000000 +0200
+++ ssb-merge/drivers/ssb/pci.c	2007-08-10 13:38:43.000000000 +0200
@@ -23,6 +23,10 @@
 #include "ssb_private.h"
 
 
+/* Define the following to 1 to enable a printk on each coreswitch. */
+#define SSB_VERBOSE_PCICORESWITCH_DEBUG		0
+
+
 /* Lowlevel coreswitching */
 int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
 {
@@ -61,10 +65,12 @@ int ssb_pci_switch_core(struct ssb_bus *
 	int err;
 	unsigned long flags;
 
-	ssb_dprintk(KERN_INFO PFX
-		    "Switching to %s core, index %d\n",
-		    ssb_core_name(dev->id.coreid),
-		    dev->core_index);
+#if SSB_VERBOSE_PCICORESWITCH_DEBUG
+	ssb_printk(KERN_INFO PFX
+		   "Switching to %s core, index %d\n",
+		   ssb_core_name(dev->id.coreid),
+		   dev->core_index);
+#endif
 
 	spin_lock_irqsave(&bus->bar_lock, flags);
 	err = ssb_pci_switch_coreidx(bus, dev->core_index);
Index: ssb-merge/drivers/ssb/pcmcia.c
===================================================================
--- ssb-merge.orig/drivers/ssb/pcmcia.c	2007-08-10 12:52:50.000000000 +0200
+++ ssb-merge/drivers/ssb/pcmcia.c	2007-08-10 13:38:43.000000000 +0200
@@ -21,6 +21,10 @@
 #include "ssb_private.h"
 
 
+/* Define the following to 1 to enable a printk on each coreswitch. */
+#define SSB_VERBOSE_PCMCIACORESWITCH_DEBUG		0
+
+
 int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus,
 			      u8 coreidx)
 {
@@ -91,10 +95,12 @@ int ssb_pcmcia_switch_core(struct ssb_bu
 	int err;
 	unsigned long flags;
 
-	ssb_dprintk(KERN_INFO PFX
-		    "Switching to %s core, index %d\n",
-		    ssb_core_name(dev->id.coreid),
-		    dev->core_index);
+#if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
+	ssb_printk(KERN_INFO PFX
+		   "Switching to %s core, index %d\n",
+		   ssb_core_name(dev->id.coreid),
+		   dev->core_index);
+#endif
 
 	spin_lock_irqsave(&bus->bar_lock, flags);
 	err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);

--