From: Matthew Wilcox <matthew@wil.cx>
To: "Luis R. Rodriguez" <mcgrof@gmail.com>
Cc: Nick Kossifidis <mickflemm@gmail.com>,
linux-wireless <linux-wireless@vger.kernel.org>,
ath5k-devel@lists.ath5k.org,
Stephen Hemminger <shemminger@vyatta.com>,
Kyle McMartin <kyle@mcmartin.ca>
Subject: Re: pci_set_mwi() and ath5k
Date: Wed, 4 Nov 2009 15:00:34 -0700 [thread overview]
Message-ID: <20091104220034.GI10555@parisc-linux.org> (raw)
In-Reply-To: <43e72e890911041352n3a398b41h8927387c228661c5@mail.gmail.com>
On Wed, Nov 04, 2009 at 01:52:30PM -0800, Luis R. Rodriguez wrote:
> > Even better: I just confirmation from our systems team that our legacy
> > devices and 11n PCI devices don't support MWR so I'll remove all that
> > cruft crap.
>
> I meant MWI of course.
Yes, but they don't necessarily just use cacheline size for MWI ... some
devices use cacheline size for setting up data structures. Might be
worth just checking explicitly that they don't use the cacheline size
register for anything.
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
next prev parent reply other threads:[~2009-11-04 22:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-04 20:04 pci_set_mwi() and ath5k Luis R. Rodriguez
2009-11-04 20:12 ` Nick Kossifidis
2009-11-04 21:30 ` Luis R. Rodriguez
2009-11-04 21:36 ` Luis R. Rodriguez
2009-11-04 21:52 ` Luis R. Rodriguez
2009-11-04 21:52 ` Luis R. Rodriguez
2009-11-04 22:00 ` Matthew Wilcox [this message]
2009-11-04 22:04 ` Luis R. Rodriguez
2009-11-04 22:14 ` Luis R. Rodriguez
2009-11-04 22:28 ` Luis R. Rodriguez
2009-11-04 22:29 ` Matthew Wilcox
2009-11-04 22:39 ` Luis R. Rodriguez
2009-11-04 22:31 ` Nick Kossifidis
2009-11-04 22:45 ` Luis R. Rodriguez
2009-11-04 22:47 ` Luis R. Rodriguez
2009-11-04 23:14 ` Luis R. Rodriguez
2009-11-05 0:16 ` Nick Kossifidis
2009-11-05 2:55 ` Bob Copeland
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