From: Bruno Randolf <br1@einfach.org>
To: linville@tuxdriver.com
Cc: ath5k-devel@lists.ath5k.org, linux-wireless@vger.kernel.org
Subject: [PATCH] ath5k: fix antenna div gc for <= AR5K_SREV_PHY_2413
Date: Mon, 28 Jun 2010 11:01:48 +0900 [thread overview]
Message-ID: <20100628020148.4120.24790.stgit@tt-desk> (raw)
In commit 39d5b2c83ca8904b6826a0713263a4e5a9c0730a "ath5k: update
AR5K_PHY_RESTART_DIV_GC values to match masks" i introduced a regression on PHY
chips older than AR5K_SREV_PHY_5413, which caused signal values to be about
10dB less that before. This patch reverts the AR5K_PHY_RESTART_DIV_GC values to
the same values which were effectively used before (without the bitmask
mistake). This brings signal levels back to normal on these PHY chips.
Signed-off-by: Bruno Randolf <br1@einfach.org>
---
drivers/net/wireless/ath/ath5k/phy.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index 73c4fcd..6284c38 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -1768,7 +1768,7 @@ ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
if (enable) {
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
- AR5K_PHY_RESTART_DIV_GC, 1);
+ AR5K_PHY_RESTART_DIV_GC, 4);
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
AR5K_PHY_FAST_ANT_DIV_EN);
reply other threads:[~2010-06-28 2:03 UTC|newest]
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