Re: carl9170: RX and TX interrupt callback ?

[Christian Lamparter <chunkeey@googlemail.com>]

On Monday 10 January 2011 22:24:18 Chris Pechard wrote:
> I am trying to do time measurement using carl9170 firmware side. There was some 
> interesting previous thread about clock to be used and location of the probe in 
> the code. My goal is to get a precise time from the moment a packet has been 
> transmitted (timestamp when the packet has been transmitted) and the arrival of 
> the next received packet (time when a packet has been fully received). Looking 
> though the code, there is a loop in src/main.c handling the TX/RX interrupt by 
> reading the AR9170_MAC_REG_INT_CTRL register and checking the 
> AR9170_MAC_INT_TXC/RXC bits. Pending on task to be performed in the loop, it 
> could take tens of microseconds to go through one iteration which affects the 
> measurement and resulting in having RXC timestamp smaller than TXC timestamp 
> which is clearly an issue!
are you sure, you put the right code in the right place :-D .
I've posted code for the same idea a while ago [on this mailing-list] and I
can't remember anything that weird.
 
> My current workaround is to add many check to AR9170_MAC_REG_INT_CTRL in the 
> main loop to reduce the detection latency which at least gave me better results 
> (TXC time < RXC time ) but somehow it does not seem AR9170_MAC_REG_INT_CTRL 
> register is refreshed right away when a packet is received or transmitted. I 
> would like to know if there is any way to attach a callback function  to the RXC 
> or TXC interrupt so that we get immediate notification  instead of depending on 
> a polling method.
Oh it is, or it should be easy to get an interrupt event from the MAC processor.
You just have to look through the SH2 platform docs [which are freely available
from Reneas] and setup the interrupt controller accordingly.

If you're stuck and need advice on the f/irq topic, you should definitely ask
Stephen Chen <Stephen.Chen@atheros.com> for assistance. As he's one of the
few persons who know how it works. I certainly can't...

Good Luck!
> If not, is there any way to minimize delays between the time 
> a packet is sent/received and the TXC/RXC bit flag raised in the register?
Don't forget the 802.11 is working against you.
CSMA/CA with R/S/D/P/E/IFS, [random] backoff, dynamic ACK delays and 
so much more can really spoil the day, if you are not aware that it's
there. 

Furthermore, have you tried to contact the people behind similar projects?
	Ignacy Gawedzki <i@lri.fr>
	David H. Lynch Jr. <dhlii@dlasys.net>

Especially David, since it seems that he's done with it.

Best Regards,
	Chr

PS.: you could also go a different route with OpenFWWF.