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* [PATCH 1/4] ath9k_hw: fix REG_SET_BIT and REG_CLR_BIT for multiple bits
@ 2011-03-10  0:35 Felix Fietkau
  2011-03-10  0:35 ` [PATCH 2/4] ath9k: fix stopping tx dma on reset Felix Fietkau
  0 siblings, 1 reply; 14+ messages in thread
From: Felix Fietkau @ 2011-03-10  0:35 UTC (permalink / raw)
  To: linux-wireless; +Cc: linville, lrodriguez

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
---
 drivers/net/wireless/ath/ath9k/hw.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index ef79f4c..6650fd4 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -95,9 +95,9 @@
 #define REG_READ_FIELD(_a, _r, _f) \
 	(((REG_READ(_a, _r) & _f) >> _f##_S))
 #define REG_SET_BIT(_a, _r, _f) \
-	REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
+	REG_WRITE(_a, _r, REG_READ(_a, _r) | (_f))
 #define REG_CLR_BIT(_a, _r, _f) \
-	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
+	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f))
 
 #define DO_DELAY(x) do {			\
 		if ((++(x) % 64) == 0)          \
-- 
1.7.3.2


^ permalink raw reply related	[flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] ath9k: fix stopping tx dma on reset
@ 2011-03-10  4:21 Mark Mentovai
  2011-03-10 13:20 ` Felix Fietkau
  0 siblings, 1 reply; 14+ messages in thread
From: Mark Mentovai @ 2011-03-10  4:21 UTC (permalink / raw)
  To: Felix Fietkau, linux-wireless; +Cc: linville, lrodriguez

> --- a/drivers/net/wireless/ath/ath9k/mac.c
[...]
> +bool ath9k_hw_abort_tx_dma(struct ath_hw *ah)
[...]
> +	for (q = 0; q < AR_NUM_QCU; q++) {
> +		for (i = 1000; i > 0; i--) {
> +			if (!ath9k_hw_numtxpending(ah, q))
> +				break;
> +
> +			udelay(5);
> +		}
> +	}
> +	if (!i)
> +		return false;

Awesome-looking patch set.

What’s the return value of this function supposed to mean? As written, it only returns false there’s anything left pending on the final queue. Notably, if the inner loop ran for all 999 iterations and ath9k_hw_numtxpending never returned false, the code above would effectively ignore that condition.

I’m less concerned about the return value (because it actually seems that the function could be declared void, you don’t use the return value anywhere) than I am about the REG_CLR_BIT and REG_WRITE operations that follow. It seems that you might be either missing those in cases where they should happen, or performing them in cases where they shouldn’t. Did you mean to leave AR_Q_TXD set when something is left pending on the final hardware queue?

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2011-03-10 13:20 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-03-10  0:35 [PATCH 1/4] ath9k_hw: fix REG_SET_BIT and REG_CLR_BIT for multiple bits Felix Fietkau
2011-03-10  0:35 ` [PATCH 2/4] ath9k: fix stopping tx dma on reset Felix Fietkau
2011-03-10  0:35   ` [PATCH 3/4] ath9k: fix the .flush driver op implementation Felix Fietkau
2011-03-10  0:35     ` [PATCH 4/4] ath9k: improve reliability of beacon transmission and stuck beacon handling Felix Fietkau
2011-03-10  9:46       ` Vasanthakumar Thiagarajan
2011-03-10 13:04         ` Felix Fietkau
2011-03-10 13:15           ` Felix Fietkau
2011-03-10  9:25     ` [PATCH 3/4] ath9k: fix the .flush driver op implementation Vasanthakumar Thiagarajan
2011-03-10 13:03       ` Felix Fietkau
2011-03-10  8:58   ` [PATCH 2/4] ath9k: fix stopping tx dma on reset Vasanthakumar Thiagarajan
2011-03-10  9:32     ` Vasanthakumar Thiagarajan
2011-03-10 12:47     ` Felix Fietkau
  -- strict thread matches above, loose matches on Subject: below --
2011-03-10  4:21 Mark Mentovai
2011-03-10 13:20 ` Felix Fietkau

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