From: Ping-Ke Shih <pkshih@realtek.com>
To: <kvalo@kernel.org>
Cc: <gary.chang@realtek.com>, <phhuang@realtek.com>,
<kevin_yang@realtek.com>, <linux-wireless@vger.kernel.org>
Subject: [PATCH v2 01/11] wifi: rtw89: correct PHY register offset for PHY-1
Date: Fri, 9 Feb 2024 14:52:19 +0800 [thread overview]
Message-ID: <20240209065229.34515-2-pkshih@realtek.com> (raw)
In-Reply-To: <20240209065229.34515-1-pkshih@realtek.com>
PHY-1 can be seen as a copy of PHY-0, and the difference is their base
register address, so add a function to get offset to access PHY-1.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
---
drivers/net/wireless/realtek/rtw89/phy.c | 13 +++++++++----
drivers/net/wireless/realtek/rtw89/phy.h | 1 +
drivers/net/wireless/realtek/rtw89/phy_be.c | 19 +++++++++++++++++++
3 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index 9a8f5b764617..7c2f0ba996b1 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -13,6 +13,13 @@
#include "txrx.h"
#include "util.h"
+static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
+{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+
+ return phy->phy0_phy1_offset(rtwdev, addr);
+}
+
static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
const struct rtw89_ra_report *report)
{
@@ -1633,14 +1640,11 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
}
-static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
+static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
{
u32 phy_page = addr >> 8;
u32 ofst = 0;
- if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
- return addr < 0x10000 ? 0x20000 : 0;
-
switch (phy_page) {
case 0x6:
case 0x7:
@@ -6392,6 +6396,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
.ccx = &rtw89_ccx_regs_ax,
.physts = &rtw89_physts_regs_ax,
.cfo = &rtw89_cfo_regs_ax,
+ .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
.config_bb_gain = rtw89_phy_config_bb_gain_ax,
.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
.bb_wrap_init = NULL,
diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h
index d80ddc723e86..76234daab896 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.h
+++ b/drivers/net/wireless/realtek/rtw89/phy.h
@@ -510,6 +510,7 @@ struct rtw89_phy_gen_def {
const struct rtw89_ccx_regs *ccx;
const struct rtw89_physts_regs *physts;
const struct rtw89_cfo_regs *cfo;
+ u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
void (*config_bb_gain)(struct rtw89_dev *rtwdev,
const struct rtw89_reg2_def *reg,
enum rtw89_rf_path rf_path,
diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c
index 6849438a5f3c..be0148f2b96f 100644
--- a/drivers/net/wireless/realtek/rtw89/phy_be.c
+++ b/drivers/net/wireless/realtek/rtw89/phy_be.c
@@ -78,6 +78,24 @@ static const struct rtw89_cfo_regs rtw89_cfo_regs_be = {
.valid_0_mask = B_DCFO_OPT_EN_V1,
};
+static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr)
+{
+ u32 phy_page = addr >> 8;
+ u32 ofst = 0;
+
+ if ((phy_page >= 0x4 && phy_page <= 0xF) ||
+ (phy_page >= 0x20 && phy_page <= 0x2B) ||
+ (phy_page >= 0x40 && phy_page <= 0x4f) ||
+ (phy_page >= 0x60 && phy_page <= 0x6f) ||
+ (phy_page >= 0xE4 && phy_page <= 0xE5) ||
+ (phy_page >= 0xE8 && phy_page <= 0xED))
+ ofst = 0x1000;
+ else
+ ofst = 0x0;
+
+ return ofst;
+}
+
union rtw89_phy_bb_gain_arg_be {
u32 addr;
struct {
@@ -952,6 +970,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
.ccx = &rtw89_ccx_regs_be,
.physts = &rtw89_physts_regs_be,
.cfo = &rtw89_cfo_regs_be,
+ .phy0_phy1_offset = rtw89_phy0_phy1_offset_be,
.config_bb_gain = rtw89_phy_config_bb_gain_be,
.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be,
.bb_wrap_init = rtw89_phy_bb_wrap_init_be,
--
2.25.1
next prev parent reply other threads:[~2024-02-09 6:53 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-09 6:52 [PATCH v2 00/11] wifi: rtw89: enable DBCC for WiFi 7 chips by default Ping-Ke Shih
2024-02-09 6:52 ` Ping-Ke Shih [this message]
2024-02-12 15:39 ` [PATCH v2 01/11] wifi: rtw89: correct PHY register offset for PHY-1 Kalle Valo
2024-02-09 6:52 ` [PATCH v2 02/11] wifi: rtw89: load BB parameters to PHY-1 Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 03/11] wifi: rtw89: mac: return held quota of DLE when changing MAC-1 Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 04/11] wifi: rtw89: mac: correct MUEDCA setting for MAC-1 Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 05/11] wifi: rtw89: mac: reset PHY-1 hardware when going to enable/disable Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 06/11] wifi: rtw89: use PLCP information to match BSS_COLOR and AID Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 07/11] wifi: rtw89: differentiate narrow_bw_ru_dis setting according to chip gen Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 08/11] wifi: rtw89: 8922a: correct register definition and merge IO for ctrl_nbtg_bt_tx() Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 09/11] wifi: rtw89: 8922a: implement AP mode related reg for BE generation Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 10/11] wifi: rtw89: reference quota mode when setting Tx power Ping-Ke Shih
2024-02-09 6:52 ` [PATCH v2 11/11] wifi: rtw89: change qutoa to DBCC by default for WiFi 7 chips Ping-Ke Shih
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