From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AD6C15747D; Thu, 13 Mar 2025 17:05:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741885505; cv=none; b=pwnQAwiv5M5lE6B4vEszl417YUSDpnMoHnIyh+H+p+dZPKuZISkKtWli0VMRGssAhawnQ2S2C/dmvWNh7BYE5bFbe/q2snxO3bVj9TUnmF6hfbcaOWgX4iCHtrUM8gVBOBL+Jy4ESCuzcAQIk4aB0pSUZr4h6u/UAXvTh0/7Tms= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741885505; c=relaxed/simple; bh=VCw61kDDKPEEVAbOsalb7B/m4QeaA68e6JeTKmVJYao=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=d9LO2tww0lKvyNowjXIAz9unfuEq9BkUo8o0Qfj/CxLOmthYqQDLDBoeCLPKcqv9COXdH2+9RU/WeXd453YLFuoyy340frZhjzIpKx5NlKc32+t3AyCm/f2Sof6p4Z1abPAawVtNhVbnf4Wja0f2YGICltUYuknFNtszRFA+5GM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oJQAnSaJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oJQAnSaJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A13AC4CEDD; Thu, 13 Mar 2025 17:05:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741885504; bh=VCw61kDDKPEEVAbOsalb7B/m4QeaA68e6JeTKmVJYao=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=oJQAnSaJypK+GCzi7ekXGTtSCo21nK0djOltX04Hrp3bBKT4Hn1eGhXuaUybes1es bk5Sw7XwbSw/ig1HL1V8NZzlUFt01Pxr2NX6honv21EYaU5UmKPsWpQLsoc143QGFE YH0VDr7b1wMJZuuDBqt8G4rKz2PTmh4P2RLcc6+qnF/Y5NVF7PgEmanbYMvE2GK5yq aKxrVLwzZO7qV3SyAhpsYTYY0y59yC2aFp8jOGB5SO7tqcEnpjdB37Xn8qAfDGCknG 6nmgB2vArGJOMhFP2JwiRLc7ztFWDgmfAJrNhaewIz8yeKI5PrhSLbIPhnk7Mi5V5B GOSBx0CV/uGOw== Date: Thu, 13 Mar 2025 12:05:03 -0500 From: Bjorn Helgaas To: Krishna Chaitanya Chundru Cc: Bjorn Helgaas , Ilpo =?utf-8?B?SsOkcnZpbmVu?= , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Johannes Berg , Jeff Johnson , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, quic_pyarlaga@quicinc.com, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, Jeff Johnson Subject: Re: [PATCH v2 06/10] bus: mhi: host: Add support to read MHI capabilities Message-ID: <20250313170503.GA738903@bhelgaas> Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250313-mhi_bw_up-v2-6-869ca32170bf@oss.qualcomm.com> On Thu, Mar 13, 2025 at 05:10:13PM +0530, Krishna Chaitanya Chundru wrote: > From: Vivek Pernamitta > > As per MHI spec sec 6.6, MHI has capability registers which are located > after the ERDB array. The location of this group of registers is > indicated by the MISCOFF register. Each capability has a capability ID to > determine which functionality is supported and each capability will point > to the next capability supported. > > Add a basic function to read those capabilities offsets. Sounds like an MHI version of pci_find_capability(). Maybe could be named similarly too? > Signed-off-by: Vivek Pernamitta > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/bus/mhi/common.h | 4 ++++ > drivers/bus/mhi/host/init.c | 29 +++++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h > index dda340aaed95..eedac801b800 100644 > --- a/drivers/bus/mhi/common.h > +++ b/drivers/bus/mhi/common.h > @@ -16,6 +16,7 @@ > #define MHICFG 0x10 > #define CHDBOFF 0x18 > #define ERDBOFF 0x20 > +#define MISCOFF 0x24 > #define BHIOFF 0x28 > #define BHIEOFF 0x2c > #define DEBUGOFF 0x30 > @@ -113,6 +114,9 @@ > #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) > #define MHISTATUS_SYSERR_MASK BIT(2) > #define MHISTATUS_READY_MASK BIT(0) > +#define MISC_CAP_MASK GENMASK(31, 0) > +#define CAP_CAPID_MASK GENMASK(31, 24) > +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) > > /* Command Ring Element macros */ > /* No operation command */ > diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c > index a9b1f8beee7b..0b14b665ed15 100644 > --- a/drivers/bus/mhi/host/init.c > +++ b/drivers/bus/mhi/host/init.c > @@ -467,6 +467,35 @@ int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) > return ret; > } > > +static int mhi_get_capability_offset(struct mhi_controller *mhi_cntrl, u32 capability, u32 *offset) > +{ > + u32 val, cur_cap, next_offset; > + int ret; > + > + /* get the 1st supported capability offset */ > + ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MISCOFF, > + MISC_CAP_MASK, offset); > + if (ret) > + return ret; > + do { > + if (*offset >= mhi_cntrl->reg_len) > + return -ENXIO; > + > + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, *offset, &val); > + if (ret) > + return ret; > + > + cur_cap = FIELD_PREP(CAP_CAPID_MASK, val); > + next_offset = FIELD_PREP(CAP_NEXT_CAP_MASK, val); > + if (cur_cap == capability) > + return 0; > + > + *offset = next_offset; > + } while (next_offset); > + > + return -ENXIO; > +} > + > int mhi_init_mmio(struct mhi_controller *mhi_cntrl) > { > u32 val; > > -- > 2.34.1 >