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From: Ping-Ke Shih <pkshih@realtek.com>
To: <linux-wireless@vger.kernel.org>
Cc: <echuang@realtek.com>, <phhuang@realtek.com>
Subject: [PATCH rtw-next 06/12] wifi: rtw89: phy: abstract BB wrap registers to share initial flow
Date: Wed, 14 Jan 2026 09:39:44 +0800	[thread overview]
Message-ID: <20260114013950.19704-7-pkshih@realtek.com> (raw)
In-Reply-To: <20260114013950.19704-1-pkshih@realtek.com>

BB wrap registers are to configure TX power in MAC register domain, but
they are controlled and designed by BB layer. Since coming chips use
different register address, add a struct to define them.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
---
 drivers/net/wireless/realtek/rtw89/phy.c    |  1 +
 drivers/net/wireless/realtek/rtw89/phy.h    |  6 ++++++
 drivers/net/wireless/realtek/rtw89/phy_be.c | 20 ++++++++++++++++++--
 drivers/net/wireless/realtek/rtw89/reg.h    |  2 ++
 4 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index 099c0e0ae7b6..dbbbac1d9e3e 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -8229,6 +8229,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
 	.ccx = &rtw89_ccx_regs_ax,
 	.physts = &rtw89_physts_regs_ax,
 	.cfo = &rtw89_cfo_regs_ax,
+	.bb_wrap = NULL,
 	.phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
 	.config_bb_gain = rtw89_phy_config_bb_gain_ax,
 	.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h
index f28580689626..0834569278cd 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.h
+++ b/drivers/net/wireless/realtek/rtw89/phy.h
@@ -460,6 +460,11 @@ struct rtw89_cfo_regs {
 	u32 valid_0_mask;
 };
 
+struct rtw89_bb_wrap_regs {
+	u32 pwr_macid_lmt;
+	u32 pwr_macid_path;
+};
+
 enum rtw89_bandwidth_section_num_ax {
 	RTW89_BW20_SEC_NUM_AX = 8,
 	RTW89_BW40_SEC_NUM_AX = 4,
@@ -537,6 +542,7 @@ struct rtw89_phy_gen_def {
 	const struct rtw89_ccx_regs *ccx;
 	const struct rtw89_physts_regs *physts;
 	const struct rtw89_cfo_regs *cfo;
+	const struct rtw89_bb_wrap_regs *bb_wrap;
 	u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
 	void (*config_bb_gain)(struct rtw89_dev *rtwdev,
 			       const struct rtw89_reg2_def *reg,
diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c
index 33c28a1666d4..e333c3eb1e9b 100644
--- a/drivers/net/wireless/realtek/rtw89/phy_be.c
+++ b/drivers/net/wireless/realtek/rtw89/phy_be.c
@@ -160,6 +160,16 @@ static const struct rtw89_cfo_regs rtw89_cfo_regs_be_v1 = {
 	.valid_0_mask = B_DCFO_OPT_EN_BE,
 };
 
+static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be = {
+	.pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE,
+	.pwr_macid_path = R_BE_PWR_MACID_PATH_BASE,
+};
+
+static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be_v1 = {
+	.pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE_V1,
+	.pwr_macid_path = R_BE_PWR_MACID_PATH_BASE_V1,
+};
+
 static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr)
 {
 	u32 phy_page = addr >> 8;
@@ -406,9 +416,11 @@ static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev)
 static
 void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev)
 {
+	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+	const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap;
 	u32 macid_idx, cr, base_macid_lmt, max_macid = 32;
 
-	base_macid_lmt = R_BE_PWR_MACID_LMT_BASE;
+	base_macid_lmt = bb_wrap->pwr_macid_lmt;
 
 	for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) {
 		cr = base_macid_lmt + macid_idx;
@@ -419,8 +431,10 @@ void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev)
 static
 void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev)
 {
+	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+	const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap;
+	u32 cr = bb_wrap->pwr_macid_path;
 	int i, max_macid = 32;
-	u32 cr = R_BE_PWR_MACID_PATH_BASE;
 
 	for (i = 0; i < max_macid; i++, cr += 4)
 		rtw89_write32(rtwdev, cr, 0x03C86000);
@@ -1119,6 +1133,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
 	.ccx = &rtw89_ccx_regs_be,
 	.physts = &rtw89_physts_regs_be,
 	.cfo = &rtw89_cfo_regs_be,
+	.bb_wrap = &rtw89_bb_wrap_regs_be,
 	.phy0_phy1_offset = rtw89_phy0_phy1_offset_be,
 	.config_bb_gain = rtw89_phy_config_bb_gain_be,
 	.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be,
@@ -1139,6 +1154,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = {
 	.ccx = &rtw89_ccx_regs_be_v1,
 	.physts = &rtw89_physts_regs_be_v1,
 	.cfo = &rtw89_cfo_regs_be_v1,
+	.bb_wrap = &rtw89_bb_wrap_regs_be_v1,
 	.phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1,
 	.config_bb_gain = rtw89_phy_config_bb_gain_be,
 	.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1,
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index fe51af1ecb4a..815b7d08663e 100644
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -6365,7 +6365,9 @@
 #define B_BE_PTA_GNT_BT1_BB_SWCTRL BIT(0)
 
 #define R_BE_PWR_MACID_PATH_BASE 0x0E500
+#define R_BE_PWR_MACID_PATH_BASE_V1 0x1C000
 #define R_BE_PWR_MACID_LMT_BASE 0x0ED00
+#define R_BE_PWR_MACID_LMT_BASE_V1 0x1C800
 
 #define R_BE_CMAC_FUNC_EN 0x10000
 #define R_BE_CMAC_FUNC_EN_C1 0x14000
-- 
2.25.1


  parent reply	other threads:[~2026-01-14  1:40 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-14  1:39 [PATCH rtw-next 00/12] wifi: rtw89: refactor PHY flow/setting for RTL8922D Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 01/12] wifi: rtw89: mac: clear global interrupt right after power-on Ping-Ke Shih
2026-01-22  1:54   ` Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 02/12] wifi: rtw89: phy: add {read,write}_rf_v3 for RTL8922D Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 03/12] wifi: rtw89: phy: add ops rtw89_phy_gen_be_v1 " Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 04/12] wifi: rtw89: phy: abstract start address and EHT of PHY status bitmap Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 05/12] wifi: rtw89: phy: extend register to read history 2 of PHY env_monitor Ping-Ke Shih
2026-01-14  1:39 ` Ping-Ke Shih [this message]
2026-01-14  1:39 ` [PATCH rtw-next 07/12] wifi: rtw89: phy: update bb wrapper TPU init Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 08/12] wifi: rtw89: phy: update BB wrapper RFSI Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 09/12] wifi: rtw89: phy: write BB wrapper registers with flush Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 10/12] wifi: rtw89: phy: refine initial flow of BB wrapper Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 11/12] wifi: rtw89: phy: fix incorrect power limit by mac_id Ping-Ke Shih
2026-01-14  1:39 ` [PATCH rtw-next 12/12] wifi: rtw89: fix unable to receive probe responses under MLO connection Ping-Ke Shih

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