From: Javier Tia <floss@jetm.me>
To: Felix Fietkau <nbd@nbd.name>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Ryder Lee <ryder.lee@mediatek.com>,
Shayne Chen <shayne.chen@mediatek.com>,
Sean Wang <sean.wang@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Deren Wu <deren.wu@mediatek.com>,
Ming Yen Hsieh <mingyen.hsieh@mediatek.com>
Cc: linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, "Marcin FM" <marcin@lgic.pl>,
"Cristian-Florin Radoi" <radoi.chris@gmail.com>,
"George Salukvadze" <giosal90@gmail.com>,
"Evgeny Kapusta" <3193631@gmail.com>,
"Samu Toljamo" <samu.toljamo@gmail.com>,
"Ariel Rosenfeld" <ariel.rosenfeld.750@gmail.com>,
"Chapuis Dario" <chapuisdario4@gmail.com>,
"Thibaut François" <tibo@humeurlibre.fr>,
张旭涵 <Loong.0x00@gmail.com>
Subject: [PATCH v2 09/13] wifi: mt76: mt7925: add chip-specific DMA configuration
Date: Thu, 19 Mar 2026 16:24:25 -0600 [thread overview]
Message-ID: <20260319-mt7927-wifi-support-v2-v2-9-d627a7fad70d@jetm.me> (raw)
In-Reply-To: <20260319-mt7927-wifi-support-v2-v2-0-d627a7fad70d@jetm.me>
MT7927 uses different DMA ring indices (RX rings 4, 6, 7 vs MT7925's
0, 1, 2), a different prefetch register layout, and requires additional
GLO_CFG bits (ADDR_EXT_EN, FW_DWLD_BYPASS_DMASHDL) that must be
restored after every PM wake cycle.
Introduce struct mt792x_dma_config to parameterize per-chip DMA
differences:
- RX ring indices for MCU events, data, and auxiliary queues
- Prefetch configuration callback
- GLO_CFG quirk bits (set/clear masks applied after DMA enable)
- Pre-ring-setup hook for MT7927's SET_OWN/CLR_OWN sequence
Refactor mt7925_dma_init() to read ring indices from the config struct,
eliminating the need for a standalone mt7927_dma_init(). The single
init function handles both chips by dispatching through the config.
Update mt792x_dma_enable() to apply chip-specific GLO_CFG bits from the
config and select the correct GLO_CFG_EXT1 register address per chip.
Ring layout and prefetch values derived from Loong0x00's
reverse-engineered MT7927 driver.
Tested-by: Marcin FM <marcin@lgic.pl>
Tested-by: Cristian-Florin Radoi <radoi.chris@gmail.com>
Tested-by: George Salukvadze <giosal90@gmail.com>
Tested-by: Evgeny Kapusta <3193631@gmail.com>
Tested-by: Samu Toljamo <samu.toljamo@gmail.com>
Tested-by: Ariel Rosenfeld <ariel.rosenfeld.750@gmail.com>
Tested-by: Chapuis Dario <chapuisdario4@gmail.com>
Tested-by: Thibaut François <tibo@humeurlibre.fr>
Tested-by: 张旭涵 <Loong.0x00@gmail.com>
Signed-off-by: Javier Tia <floss@jetm.me>
---
drivers/net/wireless/mediatek/mt76/mt7925/pci.c | 137 +++++++++++++++++++++--
drivers/net/wireless/mediatek/mt76/mt792x.h | 21 ++++
drivers/net/wireless/mediatek/mt76/mt792x_dma.c | 68 +++++------
drivers/net/wireless/mediatek/mt76/mt792x_regs.h | 12 ++
4 files changed, 198 insertions(+), 40 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
index 604c0e9ae7ba..415194a440f8 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c
@@ -210,17 +210,128 @@ static u32 mt7925_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
return dev->bus_ops->rmw(mdev, addr, mask, val);
}
+/* MT7927 uses different RX ring indices than MT7925 */
+enum mt7927_rxq_id {
+ MT7927_RXQ_BAND0 = 4,
+ MT7927_RXQ_MCU_WM = 6,
+ MT7927_RXQ_DATA2 = 7,
+};
+
+#define PREFETCH(base, depth) ((base) << 16 | (depth))
+
+static void mt7925_dma_prefetch(struct mt792x_dev *dev)
+{
+ /* rx ring */
+ mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x4));
+ mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0040, 0x4));
+ mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x0080, 0x4));
+ mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x00c0, 0x4));
+ /* tx ring */
+ mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0100, 0x10));
+ mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x0200, 0x10));
+ mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x0300, 0x10));
+ mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x0400, 0x10));
+ mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0500, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0540, 0x4));
+}
+
+static void mt7927_dma_prefetch(struct mt792x_dev *dev)
+{
+ /* Trigger prefetch controller reset before reprogramming */
+ mt76_wr(dev, MT_WFDMA_PREFETCH_CTRL,
+ mt76_rr(dev, MT_WFDMA_PREFETCH_CTRL));
+ /* MT7927 uses packed prefetch registers */
+ mt76_wr(dev, MT_WFDMA_PREFETCH_CFG0, 0x660077);
+ mt76_wr(dev, MT_WFDMA_PREFETCH_CFG1, 0x1100);
+ mt76_wr(dev, MT_WFDMA_PREFETCH_CFG2, 0x30004f);
+ mt76_wr(dev, MT_WFDMA_PREFETCH_CFG3, 0x542200);
+ /* per-ring EXT_CTRL */
+ mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0x0000, 0x8));
+ mt76_wr(dev, MT_WFDMA0_RX_RING6_EXT_CTRL, PREFETCH(0x0080, 0x8));
+ mt76_wr(dev, MT_WFDMA0_RX_RING7_EXT_CTRL, PREFETCH(0x0100, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0140, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0180, 0x10));
+ mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0280, 0x4));
+}
+
+static int mt7927_pre_ring_setup(struct mt792x_dev *dev)
+{
+ int ret;
+
+ /* SET_OWN -> CLR_OWN: triggers ROM to initialize WFDMA */
+ ret = mt792xe_mcu_fw_pmctrl(dev);
+ if (ret)
+ return ret;
+
+ ret = __mt792xe_mcu_drv_pmctrl(dev);
+ if (ret)
+ return ret;
+
+ /* Clear pending interrupts from previous state */
+ mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, ~0);
+
+ return 0;
+}
+
+static const struct mt792x_dma_config mt7925_dma_cfg = {
+ .rxq_band0 = MT7925_RXQ_BAND0, /* 2 */
+ .rxq_mcu_wm = MT7925_RXQ_MCU_WM, /* 0 */
+ .dma_prefetch = mt7925_dma_prefetch,
+ .glo_cfg_ext1 = MT_UWFDMA0_GLO_CFG_EXT1,
+};
+
+static const struct mt792x_dma_config mt7927_dma_cfg = {
+ .rxq_band0 = MT7927_RXQ_BAND0, /* 4 */
+ .rxq_mcu_wm = MT7927_RXQ_MCU_WM, /* 6 */
+ .rxq_data2 = MT7927_RXQ_DATA2, /* 7 */
+ .dma_prefetch = mt7927_dma_prefetch,
+ .glo_cfg_set = MT_WFDMA0_GLO_CFG_ADDR_EXT_EN |
+ MT_WFDMA0_GLO_CFG_FW_DWLD_BYPASS_DMASHDL,
+ .glo_cfg_clear = MT_WFDMA0_GLO_CFG_CSR_LBK_RX_Q_SEL_EN,
+ .glo_cfg_ext1 = MT_WFDMA0_GLO_CFG_EXT1,
+ .pre_ring_setup = mt7927_pre_ring_setup,
+};
+
static int mt7925_dma_init(struct mt792x_dev *dev)
{
+ const struct mt792x_dma_config *cfg = dev->dma_config;
int ret;
mt76_dma_attach(&dev->mt76);
- ret = mt792x_dma_disable(dev, true);
- if (ret)
- return ret;
+ if (cfg->pre_ring_setup) {
+ ret = cfg->pre_ring_setup(dev);
+ if (ret)
+ return ret;
- /* init tx queue */
+ /* Disable DMA before ring allocation */
+ mt76_clear(dev, MT_WFDMA0_GLO_CFG,
+ MT_WFDMA0_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
+ /* Ensure all DMA writes complete before polling status. */
+ wmb();
+
+ if (!mt76_poll_msec_tick(dev, MT_WFDMA0_GLO_CFG,
+ MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
+ MT_WFDMA0_GLO_CFG_RX_DMA_BUSY,
+ 0, 100, 1))
+ return -ETIMEDOUT;
+
+ mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
+ mt76_wr(dev, MT_WFDMA0_RST_DRX_PTR, ~0);
+ /* Ensure all DMA writes complete before polling status. */
+ wmb();
+ msleep(10);
+ } else {
+ ret = mt792x_dma_disable(dev, true);
+ if (ret)
+ return ret;
+ }
+
+ /* init tx queue - ring 0 */
ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7925_TXQ_BAND0,
MT7925_TX_RING_SIZE,
MT_TX_RING_BASE, NULL, 0);
@@ -241,20 +352,31 @@ static int mt7925_dma_init(struct mt792x_dev *dev)
if (ret)
return ret;
- /* rx event */
+ /* rx MCU events */
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
- MT7925_RXQ_MCU_WM, MT7925_RX_MCU_RING_SIZE,
+ cfg->rxq_mcu_wm, MT7925_RX_MCU_RING_SIZE,
MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
if (ret)
return ret;
/* rx data */
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
- MT7925_RXQ_BAND0, MT7925_RX_RING_SIZE,
+ cfg->rxq_band0, MT7925_RX_RING_SIZE,
MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
if (ret)
return ret;
+ /* rx auxiliary data (MT7927: management frames on ring 7) */
+ if (cfg->rxq_data2) {
+ ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
+ cfg->rxq_data2,
+ MT7925_RX_MCU_RING_SIZE,
+ MT_RX_BUF_SIZE,
+ MT_RX_DATA_RING_BASE);
+ if (ret)
+ return ret;
+ }
+
ret = mt76_init_queues(dev, mt792x_poll_rx);
if (ret < 0)
return ret;
@@ -373,6 +495,7 @@ static int mt7925_pci_probe(struct pci_dev *pdev,
dev->hif_ops = &mt7925_pcie_ops;
is_mt7927_hw = (pdev->device == 0x6639 || pdev->device == 0x7927);
dev->irq_map = is_mt7927_hw ? &mt7927_irq_map : &irq_map;
+ dev->dma_config = is_mt7927_hw ? &mt7927_dma_cfg : &mt7925_dma_cfg;
mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
diff --git a/drivers/net/wireless/mediatek/mt76/mt792x.h b/drivers/net/wireless/mediatek/mt76/mt792x.h
index 38790ef83e51..8a10438e26f9 100644
--- a/drivers/net/wireless/mediatek/mt76/mt792x.h
+++ b/drivers/net/wireless/mediatek/mt76/mt792x.h
@@ -203,6 +203,26 @@ struct mt792x_irq_map {
} rx;
};
+struct mt792x_dma_config {
+ /* RX ring indices */
+ u8 rxq_band0;
+ u8 rxq_mcu_wm;
+ u8 rxq_data2; /* 0 = not used */
+
+ /* Prefetch configuration */
+ void (*dma_prefetch)(struct mt792x_dev *dev);
+
+ /* GLO_CFG quirk bits to set/clear after DMA enable */
+ u32 glo_cfg_set;
+ u32 glo_cfg_clear;
+
+ /* GLO_CFG_EXT1 register address (chip-specific MMIO base) */
+ u32 glo_cfg_ext1;
+
+ /* Pre-ring-setup hook (NULL = not needed) */
+ int (*pre_ring_setup)(struct mt792x_dev *dev);
+};
+
#define mt792x_init_reset(dev) ((dev)->hif_ops->init_reset(dev))
#define mt792x_dev_reset(dev) ((dev)->hif_ops->reset(dev))
#define mt792x_mcu_init(dev) ((dev)->hif_ops->mcu_init(dev))
@@ -250,6 +270,7 @@ struct mt792x_dev {
struct mt76_connac_coredump coredump;
const struct mt792x_hif_ops *hif_ops;
const struct mt792x_irq_map *irq_map;
+ const struct mt792x_dma_config *dma_config;
struct work_struct ipv6_ns_work;
struct delayed_work mlo_pm_work;
diff --git a/drivers/net/wireless/mediatek/mt76/mt792x_dma.c b/drivers/net/wireless/mediatek/mt76/mt792x_dma.c
index 1ddec7788b66..4a6794ca86b9 100644
--- a/drivers/net/wireless/mediatek/mt76/mt792x_dma.c
+++ b/drivers/net/wireless/mediatek/mt76/mt792x_dma.c
@@ -90,42 +90,36 @@ EXPORT_SYMBOL_GPL(mt792x_rx_poll_complete);
#define PREFETCH(base, depth) ((base) << 16 | (depth))
static void mt792x_dma_prefetch(struct mt792x_dev *dev)
{
- if (is_mt7925(&dev->mt76)) {
- /* rx ring */
- mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0040, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x0080, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x00c0, 0x4));
- /* tx ring */
- mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0100, 0x10));
- mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x0200, 0x10));
- mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x0300, 0x10));
- mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x0400, 0x10));
- mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0500, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0540, 0x4));
- } else {
- /* rx ring */
- mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));
- /* tx ring */
- mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));
- mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));
+ /* mt7925 family uses per-chip prefetch via dma_config callback */
+ if (dev->dma_config && dev->dma_config->dma_prefetch) {
+ dev->dma_config->dma_prefetch(dev);
+ return;
}
+
+ /* mt7921/mt7922 legacy prefetch */
+ /* rx ring */
+ mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
+ mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));
+ mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));
+ mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));
+ mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));
+ /* tx ring */
+ mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));
+ mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));
}
int mt792x_dma_enable(struct mt792x_dev *dev)
{
- /* configure perfetch settings */
+ const struct mt792x_dma_config *cfg = dev->dma_config;
+
+ /* configure prefetch settings */
mt792x_dma_prefetch(dev);
/* reset dma idx */
@@ -150,8 +144,16 @@ int mt792x_dma_enable(struct mt792x_dev *dev)
mt76_set(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
- if (is_mt7925(&dev->mt76)) {
- mt76_rmw(dev, MT_UWFDMA0_GLO_CFG_EXT1, BIT(28), BIT(28));
+ /* Apply chip-specific GLO_CFG quirk bits from DMA config */
+ if (cfg) {
+ if (cfg->glo_cfg_set)
+ mt76_set(dev, MT_WFDMA0_GLO_CFG, cfg->glo_cfg_set);
+ if (cfg->glo_cfg_clear)
+ mt76_clear(dev, MT_WFDMA0_GLO_CFG, cfg->glo_cfg_clear);
+ }
+
+ if (cfg && cfg->glo_cfg_ext1) {
+ mt76_rmw(dev, cfg->glo_cfg_ext1, BIT(28), BIT(28));
mt76_set(dev, MT_WFDMA0_INT_RX_PRI, 0x0F00);
mt76_set(dev, MT_WFDMA0_INT_TX_PRI, 0x7F00);
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt792x_regs.h b/drivers/net/wireless/mediatek/mt76/mt792x_regs.h
index a8c8d7d6f565..1b9b51d43f79 100644
--- a/drivers/net/wireless/mediatek/mt76/mt792x_regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt792x_regs.h
@@ -299,7 +299,9 @@
#define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
#define MT_WFDMA0_GLO_CFG_RX_WB_DDONE BIT(13)
#define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15)
+#define MT_WFDMA0_GLO_CFG_CSR_LBK_RX_Q_SEL_EN BIT(20)
#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
+#define MT_WFDMA0_GLO_CFG_ADDR_EXT_EN BIT(26)
#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
#define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30)
@@ -366,6 +368,16 @@
#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
+/* MT7927 packed prefetch registers */
+#define MT_WFDMA_PREFETCH_CTRL MT_WFDMA_EXT_CSR(0x30)
+#define MT_WFDMA_PREFETCH_CFG0 MT_WFDMA_EXT_CSR(0xf0)
+#define MT_WFDMA_PREFETCH_CFG1 MT_WFDMA_EXT_CSR(0xf4)
+#define MT_WFDMA_PREFETCH_CFG2 MT_WFDMA_EXT_CSR(0xf8)
+#define MT_WFDMA_PREFETCH_CFG3 MT_WFDMA_EXT_CSR(0xfc)
+
+/* MT7927 GLO_CFG extended register */
+#define MT_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)
+
#define MT_SWDEF_BASE 0x41f200
#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
#define MT_SWDEF_MODE MT_SWDEF(0x3c)
--
2.53.0
next prev parent reply other threads:[~2026-03-19 22:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-19 22:24 [PATCH v2 00/13] wifi: mt76: mt7925: add MT7927 (Filogic 380) support Javier Tia
2026-03-19 22:24 ` [PATCH v2 01/13] wifi: mt76: mt7925: fix stale pointer comparisons in change_vif_links Javier Tia
2026-03-19 22:24 ` [PATCH v2 02/13] wifi: mt76: mt7925: add 320MHz bandwidth to bss_rlm_tlv Javier Tia
2026-03-19 22:24 ` [PATCH v2 03/13] wifi: mt76: mt7925: handle 320MHz bandwidth in RXV and TXS Javier Tia
2026-03-19 22:24 ` [PATCH v2 04/13] wifi: mt76: mt7925: populate EHT 320MHz MCS map in sta_rec Javier Tia
2026-03-19 22:24 ` [PATCH v2 05/13] wifi: mt76: mt7925: advertise EHT 320MHz capabilities for 6GHz band Javier Tia
2026-03-24 19:24 ` Sean Wang
2026-03-19 22:24 ` [PATCH v2 06/13] wifi: mt76: mt7925: add MT7927 chip ID helpers Javier Tia
2026-03-19 22:24 ` [PATCH v2 07/13] wifi: mt76: mt7925: add MT7927 firmware paths Javier Tia
2026-03-19 22:24 ` [PATCH v2 08/13] wifi: mt76: mt7925: use irq_map for chip-specific interrupt handling Javier Tia
2026-03-19 22:24 ` Javier Tia [this message]
2026-03-19 22:24 ` [PATCH v2 10/13] wifi: mt76: mt7925: add MT7927 hardware initialization Javier Tia
2026-03-19 22:24 ` [PATCH v2 11/13] wifi: mt76: mt7925: fix band_idx for stable 5GHz/6GHz operation Javier Tia
2026-03-19 22:24 ` [PATCH v2 12/13] wifi: mt76: mt7925: enable low power support for MT7927 Javier Tia
2026-03-19 22:24 ` [PATCH v2 13/13] wifi: mt76: mt7925: enable MT7927 PCI device IDs Javier Tia
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