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[60.242.93.14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed80df96sm3595073b3a.54.2026.04.29.21.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 21:57:31 -0700 (PDT) From: Lachlan Hodges To: johannes@sipsolutions.net, Lachlan Hodges , Dan Callaghan , Arien Judge Cc: ayman.grais@morsemicro.com, linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH wireless-next v2 11/31] wifi: mm81x: add hw.h Date: Thu, 30 Apr 2026 14:55:37 +1000 Message-ID: <20260430045615.334669-12-lachlan.hodges@morsemicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> References: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit (Patches split per file for review, will be a single commit alongside SDIO ids once review is complete. See cover letter for more information) Signed-off-by: Lachlan Hodges --- drivers/net/wireless/morsemicro/mm81x/hw.h | 176 +++++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 drivers/net/wireless/morsemicro/mm81x/hw.h diff --git a/drivers/net/wireless/morsemicro/mm81x/hw.h b/drivers/net/wireless/morsemicro/mm81x/hw.h new file mode 100644 index 000000000000..e22948f037bf --- /dev/null +++ b/drivers/net/wireless/morsemicro/mm81x/hw.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2026 Morse Micro + */ + +#ifndef _MM81X_HW_H_ +#define _MM81X_HW_H_ + +#include +#include "core.h" +#include "command_defs.h" + +/* This should be at a fixed location for a family of chipset */ +#define MM8108_REG_CHIP_ID 0x00002d20 + +#define MM81X_SDIO_RW_ADDR_BOUNDARY_MASK ((u32)0xFFFF0000) + +#define MM81X_CONFIG_ACCESS_1BYTE 0 +#define MM81X_CONFIG_ACCESS_2BYTE 1 +#define MM81X_CONFIG_ACCESS_4BYTE 2 + +#define MM81X_REG_TRGR_BASE(mors) ((mors)->regs->trgr_base_address) +#define MM81X_REG_TRGR1_STS(mors) (MM81X_REG_TRGR_BASE(mors) + 0x00) +#define MM81X_REG_TRGR1_SET(mors) (MM81X_REG_TRGR_BASE(mors) + 0x04) +#define MM81X_REG_TRGR1_CLR(mors) (MM81X_REG_TRGR_BASE(mors) + 0x08) +#define MM81X_REG_TRGR1_EN(mors) (MM81X_REG_TRGR_BASE(mors) + 0x0C) +#define MM81X_REG_TRGR2_STS(mors) (MM81X_REG_TRGR_BASE(mors) + 0x10) +#define MM81X_REG_TRGR2_SET(mors) (MM81X_REG_TRGR_BASE(mors) + 0x14) +#define MM81X_REG_TRGR2_CLR(mors) (MM81X_REG_TRGR_BASE(mors) + 0x18) +#define MM81X_REG_TRGR2_EN(mors) (MM81X_REG_TRGR_BASE(mors) + 0x1C) + +#define MM81X_REG_INT_BASE(mors) ((mors)->regs->irq_base_address) +#define MM81X_REG_INT1_STS(mors) (MM81X_REG_INT_BASE(mors) + 0x00) +#define MM81X_REG_INT1_SET(mors) (MM81X_REG_INT_BASE(mors) + 0x04) +#define MM81X_REG_INT1_CLR(mors) (MM81X_REG_INT_BASE(mors) + 0x08) +#define MM81X_REG_INT1_EN(mors) (MM81X_REG_INT_BASE(mors) + 0x0C) +#define MM81X_REG_INT2_STS(mors) (MM81X_REG_INT_BASE(mors) + 0x10) +#define MM81X_REG_INT2_SET(mors) (MM81X_REG_INT_BASE(mors) + 0x14) +#define MM81X_REG_INT2_CLR(mors) (MM81X_REG_INT_BASE(mors) + 0x18) +#define MM81X_REG_INT2_EN(mors) (MM81X_REG_INT_BASE(mors) + 0x1C) + +#define MM81X_REG_CHIP_ID(mors) ((mors)->regs->chip_id_address) + +#define MM81X_REG_MSI(mors) ((mors)->regs->msi_address) +#define MM81X_REG_MSI_HOST_INT(mors) ((mors)->regs->msi_value) + +#define MM81X_REG_HOST_MAGIC_VALUE(mors) ((mors)->regs->magic_num_value) + +#define MM81X_REG_RESET(mors) ((mors)->regs->cpu_reset_address) +#define MM81X_REG_RESET_VALUE(mors) ((mors)->regs->cpu_reset_value) + +#define MM81X_REG_HOST_MANIFEST_PTR(mors) ((mors)->regs->manifest_ptr_address) + +#define MM81X_REG_EARLY_CLK_CTRL_VALUE(mors) \ + ((mors)->regs->early_clk_ctrl_value) + +#define MM81X_REG_CLK_CTRL(mors) ((mors)->regs->clk_ctrl_address) +#define MM81X_REG_CLK_CTRL_VALUE(mors) ((mors)->regs->clk_ctrl_value) + +#define MM81X_REG_BOOT_ADDR(mors) ((mors)->regs->boot_address) +#define MM81X_REG_BOOT_ADDR_VALUE(mors) ((mors)->regs->boot_value) + +#define MM81X_REG_AON_ADDR(mors) ((mors)->regs->aon) +#define MM81X_REG_AON_COUNT(mors) ((mors)->regs->aon_count) +#define MM81X_REG_AON_LATCH_ADDR(mors) ((mors)->regs->aon_latch) +#define MM81X_REG_AON_LATCH_MASK(mors) ((mors)->regs->aon_latch_mask) +#define MM81X_REG_AON_USB_RESET(mors) ((mors)->regs->aon_reset_usb_value) + +/* Bit 17 to 24 reserved for the beacon VIF 0 to 7 interrupts */ +#define MM81X_INT_BEACON_VIF_MASK_ALL (GENMASK(24, 17)) +#define MM81X_INT_BEACON_BASE_NUM (17) + +/* PV0 NDP probe interrupts (VIF 0 and 1). */ +#define MM81X_INT_NDP_PROBE_REQ_PV0_VIF_MASK_ALL (GENMASK(26, 25)) +#define MM81X_INT_NDP_PROBE_REQ_PV0_BASE_NUM (25) + +/* Bit 27 Chip to Host stop notify */ +#define MM81X_INT_HW_STOP_NOTIFICATION_NUM (27) +#define MM81X_INT_HW_STOP_NOTIFICATION BIT(MM81X_INT_HW_STOP_NOTIFICATION_NUM) + +#define CHIP_TYPE_SILICON 0x0 + +/* Chip ID */ +#define MM8108XX_ID 0x9 + +/* Chip Rev */ +#define MM8108B2_REV 0x8 + +/* Chip Rev String */ +#define MM8108B_STRING "b" +#define MM8108B2_REV_STRING MM8108B_STRING "2" + +/* Chip ID for MM8108 */ +#define MM8108B2_ID \ + MM81X_DEVICE_ID(MM8108XX_ID, MM8108B2_REV, CHIP_TYPE_SILICON) + +#define FW_RAM_ONLY_STRING "" +#define FW_ROM_LINKED_STRING "-rl" +#define FW_ROM_ALL_STRING "-ro" + +/* + * Minimum time we must wait between attempting to reload the HW after a + * stop notification + */ +#define HW_RELOAD_AFTER_STOP_WINDOW 5 + +enum host_table_firmware_flags { + MM81X_FW_FLAGS_SUPPORT_S1G = BIT(0), + MM81X_FW_FLAGS_BUSY_ACTIVE_LOW = BIT(1), + MM81X_FW_FLAGS_REPORTS_TX_BEACON_COMPLETION = BIT(2), + MM81X_FW_FLAGS_SUPPORT_HW_SCAN = BIT(3), + MM81X_FW_FLAGS_SUPPORT_CHIP_HALT_IRQ = BIT(4), +}; + +struct host_table { + __le32 magic_number; + __le32 fw_version_number; + __le32 host_flags; + __le32 firmware_flags; + __le32 memcmd_cmd_addr; + __le32 memcmd_resp_addr; + __le32 ext_host_tbl_addr; +} __packed; + +struct mm81x_regs { + u32 chip_id_address; + u32 irq_base_address; + u32 trgr_base_address; + u32 cpu_reset_address; + u32 cpu_reset_value; + u32 msi_address; + u32 msi_value; + u32 manifest_ptr_address; + u32 magic_num_value; + u32 clk_ctrl_address; + u32 clk_ctrl_value; + u32 early_clk_ctrl_value; + u32 boot_address; + u32 boot_value; + u32 pager_base_address; + u32 aon_latch; + u32 aon_latch_mask; + u32 aon_reset_usb_value; + u32 aon; + u8 aon_count; +}; + +int mm81x_hw_otp_get_board_type(struct mm81x *mors); +bool mm81x_hw_otp_valid_board_type(u32 board_type); +int mm81x_hw_otp_get_mac_addr(struct mm81x *mors); + +void mm81x_hw_irq_enable(struct mm81x *mors, u32 irq, bool enable); +int mm81x_hw_irq_handle(struct mm81x *mors); +void mm81x_hw_irq_clear(struct mm81x *mors); +void mm81x_hw_toggle_aon_latch(struct mm81x *mors); +void mm81x_hw_enable_burst_mode(struct mm81x *mors, const u8 burst_mode); +int mm81x_hw_digital_reset(struct mm81x *mors); +void mm81x_hw_pre_firmware_ndr_hook(struct mm81x *mors); +void mm81x_hw_post_firmware_ndr_hook(struct mm81x *mors); + +enum sdio_burst_mode { + SDIO_WORD_BURST_DISABLE = + 0, /* Intentionally duplicate to make it clear it's disabled */ + SDIO_WORD_BURST_SIZE_0 = 0, /* 000: no bursting (single 32bit word) */ + SDIO_WORD_BURST_SIZE_2 = 1, /* 001: bursts of 2 words */ + SDIO_WORD_BURST_SIZE_4 = 2, /* 010: bursts of 4 words */ + SDIO_WORD_BURST_SIZE_8 = 3, /* 011: bursts of 8 words */ + SDIO_WORD_BURST_SIZE_16 = 4, /* 100: bursts of 16 words */ + SDIO_WORD_BURST_MASK = 7, +}; + +extern const struct mm81x_regs mm8108_regs; + +void mm81x_hw_enable_stop_notifications(struct mm81x *mors, bool enable); + +#endif /* !_MM81X_HW_H_ */ -- 2.43.0