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[60.242.93.14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed80df96sm3595073b3a.54.2026.04.29.21.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 21:57:01 -0700 (PDT) From: Lachlan Hodges To: johannes@sipsolutions.net, Lachlan Hodges , Dan Callaghan , Arien Judge Cc: ayman.grais@morsemicro.com, linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH wireless-next v2 05/31] wifi: mm81x: add core.c Date: Thu, 30 Apr 2026 14:55:31 +1000 Message-ID: <20260430045615.334669-6-lachlan.hodges@morsemicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> References: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit (Patches split per file for review, will be a single commit alongside SDIO ids once review is complete. See cover letter for more information) Signed-off-by: Lachlan Hodges --- drivers/net/wireless/morsemicro/mm81x/core.c | 146 +++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 drivers/net/wireless/morsemicro/mm81x/core.c diff --git a/drivers/net/wireless/morsemicro/mm81x/core.c b/drivers/net/wireless/morsemicro/mm81x/core.c new file mode 100644 index 000000000000..b08f52921525 --- /dev/null +++ b/drivers/net/wireless/morsemicro/mm81x/core.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2026 Morse Micro + */ +#include +#include "core.h" +#include "bus.h" +#include "hif.h" +#include "mac.h" + +char board_config_file[BCF_SIZE_MAX] = ""; +module_param_string(bcf, board_config_file, BCF_SIZE_MAX, 0644); +MODULE_PARM_DESC(bcf, "BCF filename to load"); + +static int mm81x_core_attach_regs(struct mm81x *mors) +{ + int ret = 0; + + mm81x_claim_bus(mors); + ret = mm81x_reg32_read(mors, MM8108_REG_CHIP_ID, &mors->chip_id); + mm81x_release_bus(mors); + + if (ret < 0) { + dev_err(mors->dev, "failed to read chip id %d", ret); + return ret; + } + + switch (mors->chip_id) { + case (MM8108B2_ID): + mors->regs = &mm8108_regs; + mors->hif.ops = &mm81x_yaps_ops; + break; + default: + return -ENODEV; + } + + return ret; +} + +static char *mm81x_core_get_revision_string(u32 chip_id) +{ + u8 chip_rev = MM81X_DEVICE_GET_CHIP_REV(chip_id); + + switch (chip_rev) { + case MM8108B2_REV: + return MM8108B2_REV_STRING; + default: + return "??"; + } +} + +static void mm81x_core_init_mac_addr(struct mm81x *mors) +{ + int ret = mm81x_hw_otp_get_mac_addr(mors); + + if (ret || !is_valid_ether_addr(mors->macaddr)) + eth_random_addr(mors->macaddr); +} + +char *mm81x_core_get_fw_path(u32 chip_id) +{ + return kasprintf(GFP_KERNEL, + MM81X_FW_DIR "/" MM8108_FW_BASE + "%s" FW_ROM_LINKED_STRING MM81X_FW_EXT, + mm81x_core_get_revision_string(chip_id)); +} +EXPORT_SYMBOL_GPL(mm81x_core_get_fw_path); + +struct mm81x *mm81x_core_alloc(size_t priv_size, struct device *dev) +{ + return mm81x_mac_alloc(priv_size, dev); +} +EXPORT_SYMBOL_GPL(mm81x_core_alloc); + +int mm81x_core_init(struct mm81x *mors) +{ + int ret; + + set_bit(MM81X_STATE_CHIP_UNRESPONSIVE, &mors->state_flags); + set_bit(MM81X_STATE_RELOAD_FW_AFTER_START, &mors->state_flags); + + mm81x_core_init_mac_addr(mors); + + ret = mm81x_core_attach_regs(mors); + if (ret) + return ret; + + mors->chip_wq = create_singlethread_workqueue("chip_wq"); + if (!mors->chip_wq) + return -ENOMEM; + + mors->net_wq = create_singlethread_workqueue("net_wq"); + if (!mors->net_wq) { + ret = -ENOMEM; + goto err_chip_wq; + } + + ret = mm81x_hif_init(mors); + if (ret) + goto err_wqs; + + return 0; + +err_wqs: + flush_workqueue(mors->net_wq); + destroy_workqueue(mors->net_wq); + +err_chip_wq: + flush_workqueue(mors->chip_wq); + destroy_workqueue(mors->chip_wq); + + return ret; +} +EXPORT_SYMBOL_GPL(mm81x_core_init); + +int mm81x_core_register(struct mm81x *mors) +{ + return mm81x_mac_register(mors); +} +EXPORT_SYMBOL_GPL(mm81x_core_register); + +void mm81x_core_unregister(struct mm81x *mors) +{ + mm81x_mac_unregister(mors); +} +EXPORT_SYMBOL_GPL(mm81x_core_unregister); + +void mm81x_core_deinit(struct mm81x *mors) +{ + mm81x_hif_finish(mors); + flush_workqueue(mors->net_wq); + destroy_workqueue(mors->net_wq); + flush_workqueue(mors->chip_wq); + destroy_workqueue(mors->chip_wq); +} +EXPORT_SYMBOL_GPL(mm81x_core_deinit); + +void mm81x_core_free(struct mm81x *mors) +{ + mm81x_mac_free(mors); +} +EXPORT_SYMBOL_GPL(mm81x_core_free); + +MODULE_AUTHOR("Morse Micro"); +MODULE_DESCRIPTION("Driver support for Morse Micro MM81X core"); +MODULE_LICENSE("Dual BSD/GPL"); -- 2.43.0