From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7083356A12; Wed, 10 Jun 2026 19:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781120412; cv=none; b=ulAva+AjdDlirU2/ESIcsLgOWlMMTDY4Rn8myLni3lLKTOJim93G6zuS/jPHDFTWjh2YsbZ5NzvcGlHxOtjOOKKBct9IQ40QiGbk8u4HyAzDW9B0l5MfOgUXvKhjFZvrzaKPMH7uTrQRVxTwPwDO4Dw7J+JuFf/cggwZ5/I/zJ0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781120412; c=relaxed/simple; bh=akMirdh0LAgb15gP4qhHFME00myVqXMkicFEVvX0blA=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=ggfEGmPL+yi+iArXSRmz5oU5GGST5BDzj3Dgythtq5snXhLWkKMCROYNrXg71OTDasOcmnYC3E1HVYCH4ghHirwmc2p0FePXKSh2/mbG8Az0O3Wde72cp6x9dO3pFRFFaayJHGZpLLVWv4FaH+0HqZcW9CPtsRRUVxujdukz00I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fuMIkcdD; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fuMIkcdD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46B231F00893; Wed, 10 Jun 2026 19:40:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781120411; bh=hU4IFAsCcxyohAC1uRq1LnazIL9Yv+87ae0nhmv5w/w=; h=Date:From:To:Cc:Subject:In-Reply-To; b=fuMIkcdDIet4CZe8638VWQL4JFeHHAUP8aGPm0y/OUNfRu7oRuyobu308+m4CWYby x04kSR8CWKYXUWx9EKINlOlOBAjtE++to2622W6NiU+kKWW6WzRf2mRNNawRVMRoQJ FRiQTfjW8awttH9aBnO6ievQxb49J78gbdbWvuvkzuPFdI04MSC/zjJnAg6qt6YW9K ymHozcyl9AV43dbS/J23W7nCAn/XWAE51nq+OQGMKEa2j+Q49WTrBzOOPITBafgc8I XUyaJKvlZ25QbHDhbTyQgA8T1VSJw7H8tuMvOA/nZWEsyitKi8cYdcuZcAGmribmhl Y4AaIXlbT/2OA== Date: Wed, 10 Jun 2026 14:40:10 -0500 From: Bjorn Helgaas To: Jose Ignacio Tornos Martinez Cc: bhelgaas@google.com, alex@shazbot.org, jjohnson@kernel.org, mani@kernel.org, linux-pci@vger.kernel.org, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, ath12k@lists.infradead.org, mhi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 3/3] PCI: Disable broken bus reset on Qualcomm devices Message-ID: <20260610194010.GA376413@bhelgaas> Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260609163649.319755-4-jtornosm@redhat.com> On Tue, Jun 09, 2026 at 06:36:49PM +0200, Jose Ignacio Tornos Martinez wrote: > Some Qualcomm PCIe devices (WCN6855/WCN7850 WiFi cards, SDX62/SDX65 modems) > do not properly support Secondary Bus Reset (SBR). > > Testing confirms this is device-specific, not deployment-specific: > MediaTek MT7925e successfully uses bus reset through the same passive > M.2-to-PCIe adapters where Qualcomm devices fail, proving PERST# is > properly wired through the adapters. > > This quirk acts as a safety net, preventing the broken bus reset from being > attempted if users override reset methods (device_specific or d3cold when > available) via sysfs. > > Signed-off-by: Jose Ignacio Tornos Martinez Applied this patch (3/3 only) to pci/virtualization for v7.2, thanks! It looks like the D3cold parts are still being ironed out. > --- > v8: code unchanged from v7 > v7: https://lore.kernel.org/all/20260603105853.326290-4-jtornosm@redhat.com/ > > drivers/pci/quirks.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index 000000000000..111111111111 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -3789,6 +3789,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1103, quirk_no_bus_reset); /* WCN6855 */ > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1107, quirk_no_bus_reset); /* WCN7850 */ > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x0308, quirk_no_bus_reset); /* SDX62/SDX65 */ > > /* > * Root port on some Cavium CN8xxx chips do not successfully complete a bus > -- > 2.53.0 >