From: Ping-Ke Shih <pkshih@realtek.com>
To: <linux-wireless@vger.kernel.org>
Cc: <gary.chang@realtek.com>, <echuang@realtek.com>
Subject: [PATCH rtw-next 13/15] wifi: rtw89: phy: add NCTL check for WiFi 7 chips
Date: Tue, 7 Jul 2026 17:10:54 +0800 [thread overview]
Message-ID: <20260707091056.42771-14-pkshih@realtek.com> (raw)
In-Reply-To: <20260707091056.42771-1-pkshih@realtek.com>
Initialize NCTL hardware and check the state before downloading NCTL.
Otherwise, the following RF calibrations relying on NCTL may fail.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
---
drivers/net/wireless/realtek/rtw89/phy.c | 1 +
drivers/net/wireless/realtek/rtw89/phy.h | 6 +++
drivers/net/wireless/realtek/rtw89/phy_be.c | 41 +++++++++++++++++++++
drivers/net/wireless/realtek/rtw89/reg.h | 6 +++
4 files changed, 54 insertions(+)
diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index dcd54be58a33..30d5741da87e 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -9010,6 +9010,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
.physts = &rtw89_physts_regs_ax,
.cfo = &rtw89_cfo_regs_ax,
.bb_wrap = NULL,
+ .nctl = NULL,
.phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
.config_bb_gain = rtw89_phy_config_bb_gain_ax,
.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h
index 532232892831..e31034377b54 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.h
+++ b/drivers/net/wireless/realtek/rtw89/phy.h
@@ -502,6 +502,11 @@ struct rtw89_bb_wrap_regs {
u32 pwr_macid_path;
};
+struct rtw89_nctl_regs {
+ u32 cfg;
+ u32 rw;
+};
+
enum rtw89_bandwidth_section_num_ax {
RTW89_BW20_SEC_NUM_AX = 8,
RTW89_BW40_SEC_NUM_AX = 4,
@@ -679,6 +684,7 @@ struct rtw89_phy_gen_def {
const struct rtw89_physts_regs *physts;
const struct rtw89_cfo_regs *cfo;
const struct rtw89_bb_wrap_regs *bb_wrap;
+ const struct rtw89_nctl_regs *nctl;
u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
void (*config_bb_gain)(struct rtw89_dev *rtwdev,
const struct rtw89_reg2_def *reg,
diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c
index ac4ce30445b3..2187b448fe75 100644
--- a/drivers/net/wireless/realtek/rtw89/phy_be.c
+++ b/drivers/net/wireless/realtek/rtw89/phy_be.c
@@ -225,6 +225,16 @@ static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be_v1 = {
.pwr_macid_path = R_BE_PWR_MACID_PATH_BASE_V1,
};
+static const struct rtw89_nctl_regs rtw89_nctl_regs_be = {
+ .cfg = R_NCTL_CFG,
+ .rw = R_NCTL_RW,
+};
+
+static const struct rtw89_nctl_regs rtw89_nctl_regs_be_v1 = {
+ .cfg = R_NCTL_CFG_BE4,
+ .rw = R_NCTL_RW_BE4,
+};
+
static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr)
{
u32 phy_page = addr >> 8;
@@ -440,6 +450,28 @@ static void rtw89_phy_config_bb_gain_be(struct rtw89_dev *rtwdev,
}
}
+static void rtw89_phy_preinit_rf_nctl_check_be(struct rtw89_dev *rtwdev)
+{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+ const struct rtw89_nctl_regs *nctl = phy->nctl;
+ int poll;
+ u32 val;
+
+ rtw89_phy_write32(rtwdev, nctl->cfg, B_NCTL_CHK_EN);
+
+ for (poll = 0; poll < 10000; poll++) {
+ rtw89_phy_write32(rtwdev, nctl->rw, B_NCTL_CHECK);
+
+ fsleep(10);
+
+ val = rtw89_phy_read32(rtwdev, nctl->rw);
+ if (val == B_NCTL_CHECK)
+ return;
+ }
+
+ rtw89_warn(rtwdev, "NCTL INIT check 0x%x[2]TIMEOUT!\n", nctl->rw);
+}
+
static void rtw89_phy_preinit_rf_nctl_be(struct rtw89_dev *rtwdev)
{
rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C0, B_GOTX_IQKDPK, 0x3);
@@ -456,6 +488,11 @@ static void rtw89_phy_preinit_rf_nctl_be(struct rtw89_dev *rtwdev)
rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_C1, B_IQK_DPK_RST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_TXRFC_C1, B_TXRFC_RST, 0x1);
}
+
+ rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_RX_CFIR_PATH_EN, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_RX_CFIR_PATH, 0x3);
+
+ rtw89_phy_preinit_rf_nctl_check_be(rtwdev);
}
static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev)
@@ -466,6 +503,8 @@ static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev)
rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_BE4, B_IQK_DPK_RST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_BE4, B_IQK_DPK_PRST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1_BE4, B_IQK_DPK_PRST, 0x1);
+
+ rtw89_phy_preinit_rf_nctl_check_be(rtwdev);
}
static u32 rtw89_phy_bb_wrap_flush_addr(struct rtw89_dev *rtwdev, u32 addr)
@@ -1905,6 +1944,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
.physts = &rtw89_physts_regs_be,
.cfo = &rtw89_cfo_regs_be,
.bb_wrap = &rtw89_bb_wrap_regs_be,
+ .nctl = &rtw89_nctl_regs_be,
.phy0_phy1_offset = rtw89_phy0_phy1_offset_be,
.config_bb_gain = rtw89_phy_config_bb_gain_be,
.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be,
@@ -1930,6 +1970,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = {
.physts = &rtw89_physts_regs_be_v1,
.cfo = &rtw89_cfo_regs_be_v1,
.bb_wrap = &rtw89_bb_wrap_regs_be_v1,
+ .nctl = &rtw89_nctl_regs_be_v1,
.phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1,
.config_bb_gain = rtw89_phy_config_bb_gain_be,
.preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1,
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 2caefb929199..4d2117de798b 100644
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -9022,6 +9022,8 @@
#define B_IQK_DPK_RST BIT(0)
#define R_TX_COLLISION_T2R_ST 0x0C70
#define B_TX_COLLISION_T2R_ST_M GENMASK(25, 20)
+#define B_RX_CFIR_PATH_EN BIT(9)
+#define B_RX_CFIR_PATH GENMASK(6, 5)
#define B_TXRX_FORCE_VAL GENMASK(9, 0)
#define R_TXGATING 0x0C74
#define B_TXGATING_EN BIT(4)
@@ -10115,6 +10117,8 @@
#define R_S1_DACKQ8 0x7E98
#define B_S1_DACKQ8_K GENMASK(15, 8)
#define R_NCTL_CFG 0x8000
+#define R_NCTL_CFG_BE4 0x38000
+#define B_NCTL_CHK_EN BIT(3)
#define B_NCTL_CFG_SPAGE GENMASK(2, 1)
#define R_NCTL_RPT 0x8008
#define B_NCTL_RPT_FLG BIT(26)
@@ -10148,6 +10152,8 @@
#define R_KIP_MOD 0x8078
#define B_KIP_MOD GENMASK(19, 0)
#define R_NCTL_RW 0x8080
+#define R_NCTL_RW_BE4 0x38080
+#define B_NCTL_CHECK BIT(2)
#define R_KIP_SYSCFG 0x8088
#define R_KIP_CLK 0x808C
#define R_DPK_IDL 0x809C
--
2.25.1
next prev parent reply other threads:[~2026-07-07 9:13 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-07 9:10 [PATCH rtw-next 00/15] wifi: rtw89: add voltage thermal protect and some random patches for RTL8922D Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 01/15] wifi: rtw89: 8922d: remove CCK bandwidth compensation Ping-Ke Shih
2026-07-12 1:55 ` Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 02/15] wifi: rtw89: 8922d: dynamic adjust channel smoothing Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 03/15] wifi: rtw89: 8922d: fix EMLSR BB switch sequence for MLO mode transition Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 04/15] wifi: rtw89: phy: fix bandedge primary channel for 2.4GHz 40MHz and 6GHz Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 05/15] wifi: rtw89: 8922d: set TX compensation by format v2 Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 06/15] wifi: rtw89: efuse: no need to export rtw89_efuse_read_ecv_be() Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 07/15] wifi: rtw89: efuse: read thermal calibration value for RTL8922D Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 08/15] wifi: rtw89: 8922d: read default digital voltage calibration values Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 09/15] wifi: rtw89: add thermal protect by digital voltage reduction Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 10/15] wifi: rtw89: 8922d: set ANA CLK enter to 500KHz Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 11/15] wifi: rtw89: 8922d: update scaling factor for RX path Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 12/15] wifi: rtw89: 8852a: fix RSSI report when average beacon RSSI is not ready Ping-Ke Shih
2026-07-07 9:10 ` Ping-Ke Shih [this message]
2026-07-07 9:10 ` [PATCH rtw-next 14/15] wifi: rtw89: unify access struct of TX power track tables Ping-Ke Shih
2026-07-07 9:10 ` [PATCH rtw-next 15/15] wifi: rtw89: set needed firmware elements for early chips transition Ping-Ke Shih
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