From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: "Bjorn Helgaas" <bhelgaas@google.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Jeff Johnson" <jjohnson@kernel.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev,
linux-wireless@vger.kernel.org, ath11k@lists.infradead.org,
qiang.yu@oss.qualcomm.com,
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Subject: [PATCH v5 3/6] PCI: Add pci_lnkctl2_bus_speed() to convert lnkctl2speed to pci_bus_speed
Date: Wed, 19 Aug 2026 18:55:54 +0530 [thread overview]
Message-ID: <20260819-bwscale-v5-3-6dea79786b37@oss.qualcomm.com> (raw)
In-Reply-To: <20260819-bwscale-v5-0-6dea79786b37@oss.qualcomm.com>
Add a exported function to convert lnkctl2speed to enum pci_bus_speed,
so that other kernel drivers can use it.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
drivers/pci/pci.c | 15 +++++++++++++++
include/linux/pci.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 77b17b13ee61..cda7d210ddbf 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5939,6 +5939,21 @@ int pcie_link_speed_mbps(struct pci_dev *pdev)
}
EXPORT_SYMBOL(pcie_link_speed_mbps);
+/**
+ * pci_lnkctl2_bus_speed - convert Link Control 2 Target Link Speed to pci_bus_speed
+ * @speed: Target Link Speed (TLS) value from Link Control 2 register (0-4 for Gen1-Gen5)
+ *
+ * Convert the Target Link Speed (TLS) field value from the Link Control 2 register
+ * to the corresponding enum pci_bus_speed.
+ *
+ * Return: pci_bus_speed corresponding to the TLS value
+ */
+enum pci_bus_speed pci_lnkctl2_bus_speed(u32 speed)
+{
+ return pcie_link_speed[speed];
+}
+EXPORT_SYMBOL(pci_lnkctl2_bus_speed);
+
/**
* pcie_bandwidth_available - determine minimum link settings of a PCIe
* device and its bandwidth limitation
diff --git a/include/linux/pci.h b/include/linux/pci.h
index d1f2d382189d..244c145af04f 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1727,6 +1727,7 @@ int pci_cfg_space_size(struct pci_dev *dev);
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
resource_size_t pcibios_window_alignment(struct pci_bus *bus,
unsigned long type);
+enum pci_bus_speed pci_lnkctl2_bus_speed(u32 speed);
#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
--
2.34.1
next prev parent reply other threads:[~2026-08-19 13:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-19 13:25 [PATCH v5 0/6] bus: mhi: host: Add support for mhi bus bw Krishna Chaitanya Chundru
2026-08-19 13:25 ` [PATCH v5 1/6] PCI/bwctrl: Set host bridge OPP and optionally disable ASPM around link retraining Krishna Chaitanya Chundru
2026-08-19 13:25 ` [PATCH v5 2/6] PCI: Export pci_set_target_speed() Krishna Chaitanya Chundru
2026-08-19 13:25 ` Krishna Chaitanya Chundru [this message]
2026-08-19 13:25 ` [PATCH v5 4/6] bus: mhi: host: Add support for Bandwidth scale Krishna Chaitanya Chundru
2026-08-19 13:25 ` [PATCH v5 5/6] wifi: ath11k: Add support for MHI bandwidth scaling Krishna Chaitanya Chundru
2026-08-19 13:25 ` [PATCH v5 6/6] PCI: qcom: Enable ASPM disabling during link retraining Krishna Chaitanya Chundru
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