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Thu, 29 Oct 2026 16:38:33 +0000 (UTC) Received: from jtornosm-thinkpadp1gen7.rmtes.csb (headnet04.pony-001.prod.iad2.dc.redhat.com [10.2.32.116]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 669011955F01; Thu, 29 Oct 2026 16:38:29 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: jgg@ziepe.ca, alex@shazbot.org, pbonzini@redhat.com, seanjc@google.com, bhelgaas@google.com, jjohnson@kernel.org Cc: johannes@sipsolutions.net, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, vkuznets@redhat.com, kevin.tian@intel.com, linux-pci@vger.kernel.org, kvm@vger.kernel.org, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, ath12k@lists.infradead.org, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v3 6/8] ath12k: add PCIe link recovery retry Date: Thu, 29 Oct 2026 17:37:11 +0100 Message-ID: <20261029163713.1366077-7-jtornosm@redhat.com> In-Reply-To: <20261029163713.1366077-1-jtornosm@redhat.com> References: <20261029163713.1366077-1-jtornosm@redhat.com> X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 When ath12k devices are passed through to VMs via PCIe passthrough, the PCIe link may not stabilize immediately after global reset due to virtualization layer timing variations. This causes MHI initialization to fail with "BHI offset: 0xffffffff is out of range" errors because the device is read before it's ready. Currently, ath12k_pci_soc_global_reset() just warns if the link is down but continues anyway, leading to inevitable MHI failures. This patch adds: 1. A retry loop (up to 5000ms) to wait for the PCIe link to recover after global reset (similar to the existing LTSSM retry logic) 2. Proper error propagation to prevent continuing with a dead link This is especially important for VM environments where timing can vary significantly from bare metal. Signed-off-by: Jose Ignacio Tornos Martinez --- v3: no modification v2: https://lore.kernel.org/all/20261011074514.515894-7-jtornosm@redhat.com/ drivers/net/wireless/ath/ath12k/pci.c | 38 ++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c index 12bbb75570f1..f7879fb48d32 100644 --- a/drivers/net/wireless/ath/ath12k/pci.c +++ b/drivers/net/wireless/ath/ath12k/pci.c @@ -181,8 +181,10 @@ static void ath12k_pci_restore_window(struct ath12k_base *ab) spin_unlock_bh(&ab_pci->window_lock); } -static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) +static int ath12k_pci_soc_global_reset(struct ath12k_base *ab) { + bool link_recovered = false; + int retries = 250; u32 val, delay; val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); @@ -206,14 +208,28 @@ static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) mdelay(delay); - val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); - if (val == 0xffffffff) - ath12k_warn(ab, "link down error during global reset\n"); + /* Wait for PCIe link to recover, especially important in VM environments + * where timing can vary significantly from bare metal. + */ + while (retries-- > 0) { + val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); + if (val != 0xffffffff) { + link_recovered = true; + break; + } + mdelay(20); + } + if (!link_recovered) { + ath12k_err(ab, "PCIe link failed to recover - device may need power cycle\n"); + return -ETIMEDOUT; + } /* Restore window register as its content is cleared during * hardware global reset, such that it aligns with host cache. */ ath12k_pci_restore_window(ab); + + return 0; } static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab) @@ -299,8 +315,10 @@ static void ath12k_pci_force_wake(struct ath12k_base *ab) mdelay(5); } -static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) +static int ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) { + int ret; + if (power_on) { ath12k_pci_enable_ltssm(ab); ath12k_pci_clear_all_intrs(ab); @@ -309,8 +327,12 @@ static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) ath12k_mhi_clear_vector(ab); ath12k_pci_clear_dbg_registers(ab); - ath12k_pci_soc_global_reset(ab); + ret = ath12k_pci_soc_global_reset(ab); + if (ret) + return ret; ath12k_mhi_set_mhictrl_reset(ab); + + return 0; } static void ath12k_pci_free_ce_irq(struct ath12k_base *ab, int num_ce) @@ -1452,7 +1474,9 @@ int ath12k_pci_power_up(struct ath12k_base *ab) ab_pci->register_window = 0; clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); - ath12k_pci_sw_reset(ab_pci->ab, true); + ret = ath12k_pci_sw_reset(ab_pci->ab, true); + if (ret) + return ret; /* Disable ASPM during firmware download due to problems switching * to AMSS state. -- 2.56.0