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Tue, 4 Mar 2025 17:10:01 +0800 Received: from RTEXMBS06.realtek.com.tw (172.21.6.99) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 4 Mar 2025 17:10:01 +0800 Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by RTEXMBS06.realtek.com.tw (172.21.6.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Tue, 4 Mar 2025 17:10:01 +0800 Received: from RTEXMBS04.realtek.com.tw ([fe80::f515:f604:42fb:a42b]) by RTEXMBS04.realtek.com.tw ([fe80::f515:f604:42fb:a42b%5]) with mapi id 15.01.2507.035; Tue, 4 Mar 2025 17:10:01 +0800 From: Ping-Ke Shih To: Mingyen Hsieh , "nbd@nbd.name" , "lorenzo@kernel.org" CC: "deren.wu@mediatek.com" , "Sean.Wang@mediatek.com" , "Leon.Yen@mediatek.com" , "Michael.Lo@mediatek.com" , "allan.wang@mediatek.com" , "Eric-SY.Chang@mediatek.com" , "km.lin@mediatek.com" , "Quan.Zhou@mediatek.com" , "Ryder.Lee@mediatek.com" , "Shayne.Chen@mediatek.com" , "linux-wireless@vger.kernel.org" , "linux-mediatek@lists.infradead.org" Subject: RE: [PATCH v2 2/6] wifi: mt76: mt7925: add EHT control support based on the CLC data Thread-Topic: [PATCH v2 2/6] wifi: mt76: mt7925: add EHT control support based on the CLC data Thread-Index: AQHbjM7PI/j8mJkHIkCfOgfmxs+AIbNir+DQ Date: Tue, 4 Mar 2025 09:10:00 +0000 Message-ID: <3c240deaec6e4a4887a8e144f558158d@realtek.com> References: <20250304062854.829194-1-mingyen.hsieh@mediatek.com> <20250304062854.829194-2-mingyen.hsieh@mediatek.com> In-Reply-To: <20250304062854.829194-2-mingyen.hsieh@mediatek.com> Accept-Language: en-US, zh-TW Content-Language: zh-TW Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Mingyen Hsieh wrote: [...] >=20 > +void mt7925_regd_be_ctrl(struct mt792x_dev *dev, u8 *alpha2) > +{ > + struct mt792x_phy *phy =3D &dev->phy; > + struct mt7925_clc_rule_v2 *rule; > + struct mt7925_clc *clc; > + bool old =3D dev->has_eht, new =3D true; > + u8 *pos; > + > + if (!phy->clc[MT792x_CLC_BE_CTRL]) > + goto out; > + > + clc =3D (struct mt7925_clc *)phy->clc[MT792x_CLC_BE_CTRL]; > + pos =3D clc->data; > + > + while (1) { while (1) could lead infinite loop unexpectedly.=20 Adding a checking of clc->len would be safer.=20 > + rule =3D (struct mt7925_clc_rule_v2 *)pos; > + > + if (rule->alpha2[0] =3D=3D alpha2[0] && > + rule->alpha2[1] =3D=3D alpha2[1]) { > + new =3D false; > + break; > + } > + > + /* Check the last one */ > + if (rule->flag && BIT(0)) > + break; > + > + pos +=3D sizeof(*rule); > + } > + > +out: > + if (old =3D=3D new) > + return; > + > + dev->has_eht =3D new; > + mt7925_set_stream_he_eht_caps(phy); > +} > + [...]