Re: [PATCH] ath9k: [DFS] add pulse width tolerance for ETSI

[Zefir Kurtisi <zefir.kurtisi@neratec.com>]

On 10/31/2012 02:32 PM, Hauke Mehrtens wrote:
> On 10/31/2012 12:23 PM, Zefir Kurtisi wrote:
>> Add 5% width tolerance for radar patterns defined by ETSI.
>>
>> Signed-off-by: Zefir Kurtisi <zefir.kurtisi@neratec.com>
>> ---
>>  .../net/wireless/ath/ath9k/dfs_pattern_detector.c  |    7 ++++++-
>>  1 files changed, 6 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/net/wireless/ath/ath9k/dfs_pattern_detector.c b/drivers/net/wireless/ath/ath9k/dfs_pattern_detector.c
>> index 3b12914..24877b0 100644
>> --- a/drivers/net/wireless/ath/ath9k/dfs_pattern_detector.c
>> +++ b/drivers/net/wireless/ath/ath9k/dfs_pattern_detector.c
>> @@ -42,10 +42,15 @@ struct radar_types {
>>  #define MIN_PPB_THRESH	50
>>  #define PPB_THRESH(PPB) ((PPB * MIN_PPB_THRESH + 50) / 100)
>>  #define PRF2PRI(PRF) ((1000000 + PRF / 2) / PRF)
>> +/* percentage of pulse width tolerance */
>> +#define WIDTH_TOLERANCE 5
>> +#define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100)
>> +#define WIDTH_UPPER(X) ((X*(100+WIDTH_TOLERANCE)+50)/100)
>                                                    ^^^
> Why are you adding 50 there? If you want to just add 5% tolerance, then
> the +50 is wrong there, but I do not know anything about radar patterns
> defined by ETSI.
> 
> Hauke
> 
Hi Hauke,

the 50 you are referring to are not the 5% defined by ETSI but used for
proper rounding in the percentage domain within that macros.

Take pattern 4 with a maximum pulse width of 30us, WIDTH_UPPER(30) then
calculates to 32. Since the HW's pulse width resolution is 1us, there is
no need to move to the nsec domain.