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From: Wojciech Dubowik <Wojciech.Dubowik@neratec.com>
To: Sujith Manoharan <sujith@msujith.org>,
	John Linville <linville@tuxdriver.com>
Cc: linux-wireless@vger.kernel.org
Subject: Re: [PATCH 5/5] ath9k: Fix TX IQ calibration for SoC chips
Date: Thu, 09 Jan 2014 13:17:17 +0100	[thread overview]
Message-ID: <52CE934D.1020400@neratec.com> (raw)
In-Reply-To: <1384665016-12022-5-git-send-email-sujith@msujith.org>

On 11/17/2013 06:10 AM, Sujith Manoharan wrote:
> From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
>
> Since calibration data reuse is not enabled in
> SoC chips, simplify the IQ calibration code.
>
> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
> ---
>   drivers/net/wireless/ath/ath9k/ar9003_calib.c | 20 ++++++++------------
>   1 file changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
> index 58eacf1..a18c3dd 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
> +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
> @@ -1255,22 +1255,19 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
>   
>   	/*
>   	 * For AR9485 or later chips, TxIQ cal runs as part of
> -	 * AGC calibration
> +	 * AGC calibration. Specifically, AR9550 in SoC chips.
>   	 */
>   	if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
> -		if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags))
> -			REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
> -				    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
> -		else
> -			REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
> -				    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
> -		txiqcal_done = run_agc_cal = true;
> -	} else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
> +		txiqcal_done = true;
>   		run_agc_cal = true;
> +	} else {
>   		sep_iq_cal = true;
> +		run_agc_cal = true;
> 	}
This code will always set run_agc to true. Does it mean you always have 
to run agc
cal no matter what since default is anyway true or it's just a typo?

if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
		txiqcal_done = true;
  		run_agc_cal = true;
} else {
  		sep_iq_cal = true;
		run_agc_cal = true;
}

The reason I am asking is that I have ran into problem with rssi reporting when calibration is ongoing.
It looks like beacon received just after IQ mismatch calibration is reported ~10-15 dB higher
than it should. I have verified power with wireshark and they are ok at antenna port.
Next beacons are reported fine. I have tried to enable disable different antennas but it doesn't seem
to affect the results.

It doesn't happen all the time but since iq calibration is on every time we are scanning it puts
wrong rssi value in scan result entry. I don't have a proof yet but it might affect probe responses
as well.

Br,
Wojtek

>   
> -skip_tx_iqcal:
> +	/*
> +	 * In the SoC family, this will run for AR9300, AR9331 and AR9340.
> +	 */
>   	if (sep_iq_cal) {
>   		txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
>   		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
> @@ -1278,6 +1275,7 @@ skip_tx_iqcal:
>   		REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
>   	}
>   
> +skip_tx_iqcal:
>   	if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
>   		/* Calibrate the AGC */
>   		REG_WRITE(ah, AR_PHY_AGC_CONTROL,
> @@ -1299,8 +1297,6 @@ skip_tx_iqcal:
>   
>   	if (txiqcal_done)
>   		ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
> -	else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
> -		ar9003_hw_tx_iq_cal_reload(ah);
>   
>   	/* Revert chainmask to runtime parameters */
>   	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);


  reply	other threads:[~2014-01-09 12:26 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-17  5:10 [PATCH 1/5] ath9k: Separate routines for PCOEM and SoC calibration Sujith Manoharan
2013-11-17  5:10 ` [PATCH 2/5] ath9k: Remove RTT/MCI code from " Sujith Manoharan
2013-11-17  5:10 ` [PATCH 3/5] ath9k: Remove unnecessary check Sujith Manoharan
2013-11-17  5:10 ` [PATCH 4/5] ath9k: Fix Carrier Leak calibration for SoC chips Sujith Manoharan
2013-11-17  5:10 ` [PATCH 5/5] ath9k: Fix TX IQ " Sujith Manoharan
2014-01-09 12:17   ` Wojciech Dubowik [this message]
2014-01-09 13:10     ` Sujith Manoharan
2014-01-09 13:35       ` Wojciech Dubowik
2014-01-09 13:52         ` Sujith Manoharan
2014-01-09 13:59           ` Wojciech Dubowik
2014-01-13 14:34             ` Wojciech Dubowik
2014-01-13 15:07               ` Sujith Manoharan
     [not found]                 ` <52D402C3.3070606@neratec.com>
     [not found]                   ` <21204.1991.201080.986559@gargle.gargle.HOWL>
2014-01-13 15:42                     ` Sujith Manoharan
2014-01-13 16:06                       ` Sujith Manoharan
2014-01-15  7:54                         ` Wojciech Dubowik
2014-01-15  8:15                           ` Sujith Manoharan
2014-01-15  8:30                             ` Wojciech Dubowik
2014-01-16 11:06                               ` Sujith Manoharan
2014-01-16 11:19                                 ` Sujith Manoharan
2014-01-16 11:44                                   ` Wojciech Dubowik
2014-01-16 21:36                                     ` Sujith Manoharan
2014-01-17  7:30                                       ` Wojciech Dubowik
2014-01-20  3:33                                         ` Sujith Manoharan

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