RE: [PATCH rtw-next 4/7] wifi: rtw88: Add rtw8814a.{c,h}

[Ping-Ke Shih <pkshih@realtek.com>]

Bitterblue Smith <rtl8821cerfe2@gmail.com> wrote:
> These contain all the logic for the RTL8814A chip.
> 
> Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>

[...]

> +static void rtw8814a_config_cck_rx_antenna_init(struct rtw_dev *rtwdev)
> +{
> +       /* CCK 2R CCA parameters */
> +
> +       /* Disable Ant diversity */
> +       rtw_write32_mask(rtwdev, REG_RXSB, BIT(15), 0x0);

#define BIT_RXSB_ANA_DIV BIT(15)

> +       /* Concurrent CCA at LSB & USB */
> +       rtw_write32_mask(rtwdev, 0xa70, BIT(7), 0);

#define REG_CCA 0xa70
#define BIT_CCA_CO BIT(7)

> +       /* RX path diversity enable */
> +       rtw_write32_mask(rtwdev, 0xa74, BIT(8), 0);

#define REG_ANTSEL 0xa74
#define BIT_ANT_BYCO BIT(8)

> +       /* r_en_mrc_antsel */
> +       rtw_write32_mask(rtwdev, 0xa14, BIT(7), 0);

#define REG_PRECTRL 0xa14
#define BIT_DIS_CO_PATHSEL BIT(7)

> +       /* MBC weighting */
> +       rtw_write32_mask(rtwdev, 0xa20, BIT(5) | BIT(4), 1);

#define REG_CCA_MF 0xa20
#define BIT_MBC_WIN GENMASK(5, 4)

> +       /* 2R CCA only */
> +       rtw_write32_mask(rtwdev, 0xa84, BIT(28), 1);

#define REG_CCKTX 0xa84
#define BIT_CMB_CCA_2R BIT(28)

Share some names, but we don't have official names for these, so if they
are conflict with others, please add suffix like V1 or something else.

[...]

> +static void rtw8814a_set_rfe_reg_24g(struct rtw_dev *rtwdev)
> +{
> +       switch (rtwdev->efuse.rfe_option) {
> +       case 2:
> +               rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x72707270);
> +               rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x72707270);
> +               rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x72707270);
> +               rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77707770);
> +
> +               rtw_write32_mask(rtwdev, 0x1ABC, 0x0ff00000, 0x72);

#define REG_RFE_INVSEL_D 0x1abc
#define BIT_RFE_SELSW0_D GENMASK(27, 20)

[...]

> +
> +static void rtw8814a_adc_clk(struct rtw_dev *rtwdev)
> +{
> +       static const u32 rxiqc_reg[2][4] = {
> +               { REG_RX_IQC_AB_A, REG_RX_IQC_AB_B,
> +                 REG_RX_IQC_AB_C, REG_RX_IQC_AB_D },
> +               { REG_RX_IQC_CD_A, REG_RX_IQC_CD_B,
> +                 REG_RX_IQC_CD_C, REG_RX_IQC_CD_D }
> +       };
> +       u32 bb_reg_8fc, bb_reg_808, rxiqc[4];
> +       u32 i = 0, mac_active = 1;
> +       u8 mac_reg_522;
> +
> +       if (rtwdev->hal.cut_version != RTW_CHIP_VER_CUT_A)
> +               return;
> +
> +       /* 1 Step1. MAC TX pause */
> +       mac_reg_522 = rtw_read8(rtwdev, REG_TXPAUSE);
> +       bb_reg_8fc = rtw_read32(rtwdev, 0x8fc);
> +       bb_reg_808 = rtw_read32(rtwdev, REG_RXPSEL);
> +       rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
> +
> +       /* 1 Step 2. Backup rxiqc & rxiqc = 0 */
> +       for (i = 0; i < 4; i++) {
> +               rxiqc[i] = rtw_read32(rtwdev, rxiqc_reg[0][i]);
> +               rtw_write32(rtwdev, rxiqc_reg[0][i], 0x0);
> +               rtw_write32(rtwdev, rxiqc_reg[1][i], 0x0);
> +       }
> +       rtw_write32_mask(rtwdev, 0xa14, 0x00000300, 0x3);

#define BIT_IQ_WGT GENMAKS(9, 8)

> +       i = 0;
> +
> +       /* 1 Step 3. Monitor MAC IDLE */
> +       rtw_write32(rtwdev, 0x8fc, 0x0);

#define REG_DBGSEL 0x8fc

> +       while (mac_active) {
> +               mac_active = rtw_read32(rtwdev, 0xfa0) & 0x803e0008;

#define REG_DBGRPT 0xfa0

> +               i++;
> +               if (i > 1000)
> +                       break;
> +       }
> +

[...]

> +
> +static void
> +rtw8814a_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
> +{
> +       struct rtw_hal *hal = &rtwdev->hal;
> +       u32 txagc_table_wd;
> +       u8 rate, pwr_index;
> +       int j;
> +
> +       for (j = 0; j < rtw_rate_size[rs]; j++) {
> +               rate = rtw_rate_section[rs][j];
> +
> +               pwr_index = hal->tx_pwr_tbl[path][rate] + 2;
> +               if (pwr_index > rtwdev->chip->max_power_index)
> +                       pwr_index = rtwdev->chip->max_power_index;
> +
> +               txagc_table_wd = 0x00801000;
> +               txagc_table_wd |= (pwr_index << 24) | (path << 8) | rate;
> +
> +               rtw_write32(rtwdev, 0x1998, txagc_table_wd);

#define REG_AGC_TBL 0x1998

> +
> +               /* first time to turn on the txagc table
> +                * second to write the addr0
> +                */
> +               if (rate == DESC_RATE1M)
> +                       rtw_write32(rtwdev, 0x1998, txagc_table_wd);
> +       }
> +}
> +

[...]

> +
> +static void rtw8814a_iqk_configure_mac(struct rtw_dev *rtwdev)
> +{
> +       rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
> +       rtw_write32_clr(rtwdev, REG_BCN_CTRL,
> +                       (BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION);
> +
> +       /* RX ante off */
> +       rtw_write8(rtwdev, REG_RXPSEL, 0x00);
> +       /* CCA off */
> +       rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xe);
> +       /* CCK RX path off */
> +       rtw_write32_set(rtwdev, 0xa14, BIT(9) | BIT(8));
> +       rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
> +       rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
> +       rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
> +       rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777);
> +       rtw_write32_mask(rtwdev, 0x1abc, 0x0ff00000, 0x77);
> +       rtw_write32_mask(rtwdev, 0x910, BIT(23) | BIT(22), 0x0);

#define REG_PSD 0x910
#define BIT_PSD_INI GENMASK(23, 22)

[...]

> diff --git a/drivers/net/wireless/realtek/rtw88/rtw8814a.h
> b/drivers/net/wireless/realtek/rtw88/rtw8814a.h
> new file mode 100644
> index 000000000000..622fcc58c134
> --- /dev/null
> +++ b/drivers/net/wireless/realtek/rtw88/rtw8814a.h
> @@ -0,0 +1,64 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
> +/* Copyright(c) 2025  Realtek Corporation
> + */
> +
> +#ifndef __RTW8814A_H__
> +#define __RTW8814A_H__
> +
> +#define RF_RCK1                0x1c

Put in reg.h

[...]