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From: Kalle Valo <kvalo@codeaurora.org>
To: Okash Khawaja <okash.khawaja@gmail.com>
Cc: joe@perches.com, linux-wireless@vger.kernel.org,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] adm8211: fix the possible pci cache line sizes inside switch-case
Date: Wed, 06 May 2015 07:59:04 +0300	[thread overview]
Message-ID: <87wq0ms3mv.fsf@kamboji.qca.qualcomm.com> (raw)
In-Reply-To: <20150505224020.GA3805@bytefire-computer> (Okash Khawaja's message of "Tue, 5 May 2015 23:40:20 +0100")

Okash Khawaja <okash.khawaja@gmail.com> writes:

> The PCI cache line size value was being compared against decimal values prefixed with 0x.
>
> Fixed the literals to use the correct hex values.
>
>
> Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>

[...]

> @@ -1101,10 +1101,10 @@ static void adm8211_hw_init(struct ieee80211_hw *dev)
>  		case  0x8:
>  			reg |= (0x1 << 14);
>  			break;
> -		case 0x16:
> +		case 0x10:
>  			reg |= (0x2 << 14);
>  			break;
> -		case 0x32:
> +		case 0x20:
>  			reg |= (0x3 << 14);
>  			break;
>  		default:

Did you test this? How certain can we be that this doesn't break
anything?

-- 
Kalle Valo

  reply	other threads:[~2015-05-06  4:59 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-05 22:40 [PATCH 2/2] adm8211: fix the possible pci cache line sizes inside switch-case Okash Khawaja
2015-05-06  4:59 ` Kalle Valo [this message]
2015-05-06  6:32   ` Okash Khawaja
2015-05-11  6:30     ` Kalle Valo
2015-05-11  8:48       ` Okash Khawaja
2015-05-11 10:38         ` Kalle Valo
2015-05-11 13:24           ` Jonas Gorski
2015-05-11 17:48             ` Okash Khawaja
2015-05-11 17:56               ` Jonas Gorski

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