Re: [PATCH v2 18/20] ath5k: update AR5K_PHY_RESTART_DIV_GC values to match masks

[Nick Kossifidis <mickflemm@gmail.com>]

2010/5/19 Bruno Randolf <br1@einfach.org>:
> #define AR5K_PHY_RESTART_DIV_GC               0x001c0000
> is 3 bit wide.
>
> The previous values of 0xc and 0x8 are 4bit wide and bigger than the mask.
>
> Writing 0 and 1 to AR5K_PHY_RESTART_DIV_GC is consistent with the comments and
> initvals we have in the HAL.
>
> Signed-off-by: Bruno Randolf <br1@einfach.org>
> ---
>  drivers/net/wireless/ath/ath5k/phy.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
> index d9506e7..2136930 100644
> --- a/drivers/net/wireless/ath/ath5k/phy.c
> +++ b/drivers/net/wireless/ath/ath5k/phy.c
> @@ -1768,13 +1768,13 @@ ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
>
>        if (enable) {
>                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
> -                               AR5K_PHY_RESTART_DIV_GC, 0xc);
> +                               AR5K_PHY_RESTART_DIV_GC, 1);
>
>                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
>                                        AR5K_PHY_FAST_ANT_DIV_EN);
>        } else {
>                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
> -                               AR5K_PHY_RESTART_DIV_GC, 0x8);
> +                               AR5K_PHY_RESTART_DIV_GC, 0);
>
>                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
>                                        AR5K_PHY_FAST_ANT_DIV_EN);
>

Acked-by: Nick Kossifidis <mickflemm@gmail.com>


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As you read this post global entropy rises. Have Fun ;-)
Nick