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Thu, 12 Mar 2026 17:30:12 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <1e96af437fa24674b353ddb530b2d8e7@realtek.com> <792645eed36041f0b3df951f1b28a08a@realtek.com> <458ed80e39734ea99610050140bb31ce@realtek.com> In-Reply-To: From: LB F Date: Fri, 13 Mar 2026 02:29:35 +0200 X-Gm-Features: AaiRm51MQDg3mHzfXYt8l7N1KSWInH5j6srRGkzTviArzhSTQm0I0YxzGHpNSZw Message-ID: Subject: Re: [BUG] wifi: rtw88: Hard system freeze on RTL8821CE when power_save is enabled (LPS/ASPM conflict) To: Ping-Ke Shih Cc: "linux-wireless@vger.kernel.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Hi Ping-Ke, I apologize for the rapid follow-up and for being perhaps a bit over-assertive in my previous email. As I continued to dig into the code, I realized that some of my interpretations of hardware registers (like REG_RX_PKT_LIMIT) and kernel serialization might be simplified compared to the real-world complexities you deal with. I'd like to reframe my previous notes as "curious observations" that I stumbled upon while testing, and I'd value your professional take on whether they are relevant: 1. RX Host-Side Validation: While searching for the 12KB limit I mentioned, I noticed that in rtw_pci_rx_napi(), the driver uses the pkt_len field from the descriptor directly for skb_put_data() without checking it against the host buffer size (RTK_PCI_RX_BUF_SIZE). Even if the hardware normally clips DMA, would it be worth adding a host-side guard there as a "hardening" measure against potentially malformed hardware reports? 2. TX Write Pointer (wp) Fetch: I noticed that in rtw_pci_tx_write_data(), get_tx_buffer_desc() fetches the wp outside the irq_lock. I wasn't sure if mac80211 guarantees that the direct TX path and the background worker threads can never collide on the same queue, but I thought it was worth mentioning just in case. 3. Memory Barriers: The wmb() point was more of an architectural observation regarding PCI best practices for non-x86 platforms. I understand x86 is quite forgiving here, but I noticed it was a pattern that stood out. Please treat these as humble suggestions from someone trying to learn the driver's internals. I didn't mean to imply these were "critical bugs" without your expert verification. Thank you for your patience with my technical excitement! Best regards, Oleksandr