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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-847833efe03sm1741991b3a.44.2026.06.29.02.44.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Jun 2026 02:44:39 -0700 (PDT) Message-ID: Date: Mon, 29 Jun 2026 17:44:35 +0800 Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10] Add device-specific reset for Qualcomm devices To: Manivannan Sadhasivam Cc: Jose Ignacio Tornos Martinez , bhelgaas@google.com, alex@shazbot.org, jjohnson@kernel.org, linux-pci@vger.kernel.org, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, ath12k@lists.infradead.org, mhi@lists.linux.dev, linux-kernel@vger.kernel.org References: <20260623183115.1585273-1-jtornosm@redhat.com> <4cdfb71b-2ef8-4985-8294-c4a29e37faa3@oss.qualcomm.com> From: Baochen Qiang Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: zlk1zwdkN7pUso7bSwfab5qAz0xPAv1u X-Authority-Analysis: v=2.4 cv=CqCPtH4D c=1 sm=1 tr=0 ts=6a423e8a cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=20KFwNOVAAAA:8 a=RRcNAnSy7hG7cj1Ejq8A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA3OCBTYWx0ZWRfX285/A6DPiuYs qCImtpZTBdLWKoJ1RCjE8sM7emfht+ggvns6017ynNj0+j+/4r8MTJkjIqr7VZRZftuYoHNSDXn +kxxfJFZnPIZ7w4qCpiqCJVynNx/ApQ= X-Proofpoint-ORIG-GUID: zlk1zwdkN7pUso7bSwfab5qAz0xPAv1u X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA3OCBTYWx0ZWRfX9xa6g4krXi69 8eG4xV1i8Ms3ch2rtEMHGO5EqvNkI379PdzFeCd8HLGJ87RYSVZQfvt9dftLZNFHlLUodNT72Iz vnINqVTn4Ic0PBwX4/Hn1hDV1pIQKTwW0JT5vqzInoxeJJyhFKKZViPrK9bV8651EVPCElrIK5T fFUOfLPb2bCLS/5gkp6QurGqxZYgb2B1RdWddLpVfKcI4IzoAUnnR4zZf8IsOFhTd7HSHMsOAjs 8J+5UtkC0KCp/WmZO1cbBRYscFvu2ZlOn9AOFBwJ47itcdWpvZeKQCBztv99rWtD4gh+88HG4sV TvpF1sc2SYelAUxOoPxQJIjV59yd02k3YXtkxDt7JTsyj0vHHjUX7tk0xLK0NDhnYY2wk5YT+Tb FMR3XCpb1PxJQ7nL/b9fbgKfS82OCXlEw7zYqY80EMM9AsffFQzObMsCpHV8Y0FofEu4/sEic5t onVAvlW3IKnoVvMPi2w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290078 On 6/25/2026 9:03 PM, Manivannan Sadhasivam wrote: > On Wed, Jun 24, 2026 at 03:47:12PM +0800, Baochen Qiang wrote: >> >> >> On 6/24/2026 2:31 AM, Jose Ignacio Tornos Martinez wrote: >>> Some Qualcomm PCIe devices (WCN6855/WCN7850 WiFi cards, SDX62/SDX65 modems) >>> lack working reset methods for VFIO passthrough scenarios. These devices >>> have no FLR capability, advertise NoSoftRst+ (blocking PM reset), and have >>> broken bus reset. >>> >>> The problem manifests in VFIO passthrough scenarios: >>> >>> - WCN6855 (17cb:1103) and WCN7850 (17cb:1107) WiFi devices: >>> Normal VM operation works fine, including clean shutdown/reboot. >>> However, when the VM terminates uncleanly (crash, force-off), VFIO >>> attempts to reset the device before it can be assigned to another VM. >>> Without a working reset method, the device remains in an undefined state, >>> preventing reuse. >>> >>> - SDX62/SDX65 (17cb:0308) 5G modems: Never successfully initialize even >>> on first VM assignment without proper reset capability. >>> >>> Add device-specific reset methods using BAR-space hardware reset registers >>> that exist in these devices: >>> >>> - WCN6855/WCN7850 WiFi devices use SoC global reset via BAR0 (sequence from >>> ath11k/ath12k driver: ath11k_pci_soc_global_reset(), ath11k_pci_sw_reset(), >>> ath11k_mhi_set_mhictrl_reset()): >>> - Write/clear reset bit at offset 0x3008 >>> - Wait for PCIe link recovery (up to 5 seconds) >>> - Clear MHI controller SYSERR status at offset 0x38 >>> >>> - SDX62/SDX65 modem devices use MHI SoC reset via BAR0 (sequence from MHI >>> driver: mhi_soc_reset(), mhi_pci_reset_prepare()): >>> - Write reset request to offset 0xb0 >>> - Wait 2 seconds for reset completion >>> >>> These are true hardware reset mechanisms (not power management or firmware >>> error recovery), providing proper device reset for VFIO scenarios. >>> >>> Testing was performed on desktop platforms with M.2 WiFi and modem cards >>> using M.2-to-PCIe adapters, including extensive force-reset cycling to >>> verify stability. >>> >>> Signed-off-by: Jose Ignacio Tornos Martinez >>> --- >>> v10: >>> - Complete redesign based on maintainer feedback (Manivannan Sadhasivam, >>> Alex Williamson): use actual hardware reset registers from >>> device drivers instead of D3hot power cycling >>> v9: https://lore.kernel.org/all/20260612142638.1243895-1-jtornosm@redhat.com/ >>> >>> drivers/pci/quirks.c | 118 +++++++++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 118 insertions(+) >>> >>> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c >>> index 431c021d7414..8ad3f214e520 100644 >>> --- a/drivers/pci/quirks.c >>> +++ b/drivers/pci/quirks.c >>> @@ -4240,6 +4240,121 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) >>> return 0; >>> } >>> >>> +#define QUALCOMM_WIFI_PCIE_SOC_GLOBAL_RESET 0x3008 >>> +#define QUALCOMM_WIFI_PCIE_SOC_GLOBAL_RESET_V BIT(0) >>> +#define QUALCOMM_WIFI_MHISTATUS 0x48 >>> +#define QUALCOMM_WIFI_MHICTRL 0x38 >>> +#define QUALCOMM_WIFI_MHICTRL_RESET_MASK 0x2 >>> + >>> +/* >>> + * Qualcomm WiFi device-specific reset using SoC global reset via BAR0 >>> + * registers. >>> + */ >>> +static int reset_qualcomm_wifi(struct pci_dev *pdev, bool probe) >>> +{ >>> + bool link_recovered = false; >>> + unsigned long timeout; >>> + void __iomem *bar; >>> + u32 val; >>> + u16 cmd; >>> + >>> + if (probe) >>> + return 0; >>> + >>> + if (pdev->current_state != PCI_D0) >>> + return -EINVAL; >>> + >>> + pci_read_config_word(pdev, PCI_COMMAND, &cmd); >>> + pci_write_config_word(pdev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); >>> + >>> + bar = pci_iomap(pdev, 0, 0); >>> + if (!bar) { >>> + pci_write_config_word(pdev, PCI_COMMAND, cmd); >>> + return -ENODEV; >>> + } >>> + >>> + val = ioread32(bar + QUALCOMM_WIFI_PCIE_SOC_GLOBAL_RESET); >> >> QUALCOMM_WIFI_PCIE_SOC_GLOBAL_RESET is beyond the first 4K bar area hence requires MHI >> wakeup before accessing, see [1]. the wakeup callback for WCN6855 is >> ath11k_pci_bus_wake_up() which calls mhi_device_get_sync(). Not sure how this can be done >> here. Maybe Mani can provide some hints? >> > > I don't think the device needs to be waken up before > QUALCOMM_WIFI_PCIE_SOC_GLOBAL_RESET. ath11k driver wakes up the device for > accessing the MHI interface I believe. Since this callback is not touching MHI, > there is no need to wakeup the device, AFAIK. MHI register space is constitute with 3 segments, with mhi offset always being 0, bhi offset 0x100 and bhie offset 0x224 (the latter two offsets are for WCN7850, but I think also apply to other devices). That said the whole MHI register space does not go beyond the first 4K region, hence wakeup is not for accessing MHI interface. > > - Mani >