* Re: [PATCH 17/19] [RFC, v2] libertas: Kconfig entry for libertas+cfg80211
From: Holger Schurig @ 2009-10-26 7:59 UTC (permalink / raw)
To: Dan Williams; +Cc: Johannes Berg, linux-wireless, John Linville
In-Reply-To: <1256316179.2164.53.camel@localhost.localdomain>
> > Well if you want to push the mesh wext bits through to cfg80211
> > (temporarily) you wouldn't even need to depend on WEXT. I'd prefer,
> > however, to not do this, and just use the cfg80211 wext handlers in
> > libertas and depend on WEXT for now.
>
> Yeah, I think it's best to handle the mesh WEXT ioctls separately for
> now. There are really only 4 of them (get/set SSID, set channel, get
> mode) that matter for mesh. The rest of the ioctls that the mesh
> interface supports get redirected to the cfg80211 handlers because they
> aren't specific to mesh.
We can reduce this to 3, because get/set channel could
simply go via cfg80211.
I'm unsure if we still need an GIWRANGE for mesh, but probably not.
Dan, you once said that you converted the MESH firmware
calls to new style commands. Do you have those around? Maybe
I can re-work them if they don't apply anymore.
--
http://www.holgerschurig.de
^ permalink raw reply
* Re: [PATCH] net: Adjust softirq raising in __napi_schedule
From: Johannes Berg @ 2009-10-26 7:58 UTC (permalink / raw)
To: Jarek Poplawski
Cc: Tilman Schmidt, David Miller, hidave.darkstar, linux-kernel, tglx,
linux-wireless, linux-ppp, netdev, paulus, Michael Buesch,
Oliver Hartkopp
In-Reply-To: <20091026075438.GB6187@ff.dom.local>
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On Mon, 2009-10-26 at 07:54 +0000, Jarek Poplawski wrote:
> > No, I wrote that I didn't know. I suppose now that I looked at it I do
> > know, and only disabling preemption is required.
>
> But netif_rx has preemption disabled most of the time (by hardirqs
> disabling). So maybe disabling preemption isn't the main reason here
> either?
Not for netpoll though, which may or may not be relevant (if I were to
venture a guess I'd say it isn't and it disables preemption to be able
to do the softirq thing)
However, I lost track now of why we're discussing this.
Basically it boils down to using netif_rx() when in (soft)irq, and
netif_rx_ni() when in process context. That could just be an
optimisation, but it's a very valid one.
johannes
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^ permalink raw reply
* Re: [PATCH 17/19] [RFC, v2] libertas: Kconfig entry for libertas+cfg80211
From: Holger Schurig @ 2009-10-26 7:55 UTC (permalink / raw)
To: Dan Williams; +Cc: linux-wireless
In-Reply-To: <1256315496.2164.47.camel@localhost.localdomain>
> Which should allow us to use cfg80211 by default, and then have
> only the LIBERTAS_MESH Kconfig option depend on WEXT. Maybe?
That would be a good idea. I always thought about a LIBERTAS_MESH
Kconfig right after persistcfg.c was added :-)
--
http://www.holgerschurig.de
^ permalink raw reply
* Re: [PATCH] net: Adjust softirq raising in __napi_schedule
From: Jarek Poplawski @ 2009-10-26 7:54 UTC (permalink / raw)
To: Johannes Berg
Cc: Tilman Schmidt, David Miller, hidave.darkstar, linux-kernel, tglx,
linux-wireless, linux-ppp, netdev, paulus, Michael Buesch,
Oliver Hartkopp
In-Reply-To: <1256543054.28230.6.camel@johannes.local>
On Mon, Oct 26, 2009 at 08:44:14AM +0100, Johannes Berg wrote:
> On Mon, 2009-10-26 at 07:41 +0000, Jarek Poplawski wrote:
>
> > > netif_rx_ni() disables preemption.
> >
> > You wrote earlier:
> >
> > > [...] the networking layer needs to have
> > > packets handed to it with softirqs disabled.
> >
> > How disabling preemption can fix something which needs softirqs
> > disabled? Could you be more precise?
>
> No, I wrote that I didn't know. I suppose now that I looked at it I do
> know, and only disabling preemption is required.
But netif_rx has preemption disabled most of the time (by hardirqs
disabling). So maybe disabling preemption isn't the main reason here
either?
Jarek P.
^ permalink raw reply
* Re: [PATCH] net: Adjust softirq raising in __napi_schedule
From: Johannes Berg @ 2009-10-26 7:44 UTC (permalink / raw)
To: Jarek Poplawski
Cc: Tilman Schmidt, David Miller, hidave.darkstar, linux-kernel, tglx,
linux-wireless, linux-ppp, netdev, paulus, Michael Buesch,
Oliver Hartkopp
In-Reply-To: <20091026074126.GA6187@ff.dom.local>
[-- Attachment #1: Type: text/plain, Size: 474 bytes --]
On Mon, 2009-10-26 at 07:41 +0000, Jarek Poplawski wrote:
> > netif_rx_ni() disables preemption.
>
> You wrote earlier:
>
> > [...] the networking layer needs to have
> > packets handed to it with softirqs disabled.
>
> How disabling preemption can fix something which needs softirqs
> disabled? Could you be more precise?
No, I wrote that I didn't know. I suppose now that I looked at it I do
know, and only disabling preemption is required.
johannes
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^ permalink raw reply
* Re: [PATCH] net: Adjust softirq raising in __napi_schedule
From: Jarek Poplawski @ 2009-10-26 7:41 UTC (permalink / raw)
To: Johannes Berg
Cc: Tilman Schmidt, David Miller, hidave.darkstar, linux-kernel, tglx,
linux-wireless, linux-ppp, netdev, paulus, Michael Buesch,
Oliver Hartkopp
In-Reply-To: <1256309191.12174.51.camel@johannes.local>
On Fri, Oct 23, 2009 at 04:46:31PM +0200, Johannes Berg wrote:
> On Fri, 2009-10-23 at 16:39 +0200, Tilman Schmidt wrote:
>
> > Strange. Then what are the two separate functions netif_rx() and
> > netif_rx_ni() for?
>
> netif_rx_ni() disables preemption.
You wrote earlier:
> [...] the networking layer needs to have
> packets handed to it with softirqs disabled.
How disabling preemption can fix something which needs softirqs
disabled? Could you be more precise?
> > > This really should be obvious. You're fixing the warning at the source
> > > of the warning, rather than the source of the problem.
> >
> > Good idea. So please do tell us where the source of the problem is.
>
> You use netif_rx_ni() instead of netif_rx() at whatever place that
> causes this problem.
This isn't a very precise description either.
Jarek P.
^ permalink raw reply
* Re: about 802.11 scan and probe request
From: Kalle Valo @ 2009-10-26 7:19 UTC (permalink / raw)
To: belle.shi; +Cc: linux-wireless
In-Reply-To: <20091026103247.2ng5wbub4ow8ok4w@webmail.yy.com>
belle.shi@yy.com writes:
> there is one question: the scan have two mode:active or passive,but
> when i run the wpa_gui, there is only scan button
Passive scan is so slow that we want to use active scan always when
possible. No need to confuse users about this, so one scan button is
enough.
> i think the active scan is to send Probe Request frame, and the
> passive scan to receive the beacon frame, is it right?
Correct.
--
Kalle Valo
^ permalink raw reply
* libertas sdio firmware
From: Johannes Berg @ 2009-10-26 7:16 UTC (permalink / raw)
To: Andrey Yurovsky; +Cc: Dan Williams, linux-wireless
[-- Attachment #1: Type: text/plain, Size: 474 bytes --]
Hi,
Was just looking at the libertas driver and noticed that the SPI part
loads firmware as such:
snprintf(helper_fw, IF_SPI_FW_NAME_MAX, "libertas/gspi%d_hlp.bin", ...
etc.
while the SDIO part just uses
ret = request_firmware(&fw, card->helper, &card->func->dev);
which ends up requesting sd8686_helper.bin instead of
libertas/sd8686_helper.bin, as far as I can tell. That means the
linux-firmware git repo won't work out of the box, I think?
johannes
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^ permalink raw reply
* Re: Rate-setting problem with Broadcom 4315
From: Larry Finger @ 2009-10-26 5:39 UTC (permalink / raw)
To: Felix Fietkau; +Cc: wireless
In-Reply-To: <4AE520F1.2070704@openwrt.org>
Actually, the rate-setting mechanism is working. If I looked at the
iwconfig rate while a transmission was in progress, the rate toggled
between 48 and 54 Mb/s. When I checked between tests, it showed 1
Mb/s, which is what fooled me.
The rc_stats table is:
rate throughput ewma prob this prob this succ/attempt
success attempts
P 1 0.9 99.9 100.0 0( 0) 314
314
2 1.8 96.9 100.0 0( 0) 15
16
5.5 4.8 95.7 100.0 0( 0) 12
12
11 9.5 99.9 100.0 0( 0) 134
138
6 5.4 95.7 100.0 0( 0) 11
11
9 8.0 95.7 100.0 0( 0) 11
11
12 10.6 95.7 100.0 0( 0) 11
11
18 15.5 95.5 100.0 0( 0) 12
13
24 20.3 95.7 100.0 0( 0) 12
12
36 29.3 96.5 96.4 0( 0) 4118
4249
T 48 37.6 96.3 100.0 23( 23) 376174
414958
t 54 36.8 84.8 81.5 62( 76) 356248
427489
Total packet count:: ideal 6627 lookaround 348
The automatic throughput is about 13 Mb/s.
Larry
^ permalink raw reply
* Re: Rate-setting problem with Broadcom 4315
From: Felix Fietkau @ 2009-10-26 4:09 UTC (permalink / raw)
To: Larry Finger; +Cc: wireless
In-Reply-To: <4AE49F0F.1060901@lwfinger.net>
Larry Finger wrote:
> When my BCM4312 (ID 4315) runs in auto rate mode, the rate stays at
> 1Mb/s. If I manually set the rate, I see a tcpperf throughput ~1/2 the
> rate that I set through a rate of 12 Mb/s. At 36 Mb/s, the rate is
> best at 15.7 Mb/s. Why does mistrel not increase the rate?
>
> The output of /sys/..../rc_stats is:
>
> finger@larrylap:~> cat
> /sys/kernel/debug/ieee80211/phy0/stations/00:14:bf:85:49:fa/rc_stats
> rate throughput ewma prob this prob this succ/attempt
> success attempts
> 1 0.9 99.1 100.0 0( 0) 3244
> 3282
> 2 1.8 95.7 100.0 0( 0) 12
> 12
> 5.5 4.8 95.7 100.0 0( 0) 12
> 12
> 11 9.2 96.8 100.0 0( 0) 12
> 12
> P 6 5.6 99.9 100.0 0( 0) 58
> 58
> 9 8.0 95.7 100.0 0( 0) 11
> 11
> 12 10.6 95.7 100.0 0( 0) 12
> 12
> 18 15.7 96.6 100.0 0( 0) 14
> 15
> 24 20.3 95.7 100.0 0( 0) 11
> 11
> 36 29.0 95.4 94.5 0( 0) 1602
> 1670
> T 48 38.7 99.2 100.0 1( 1) 32147
> 37752
> t 54 32.9 75.9 100.0 0( 0) 8775
> 12788
>
> Total packet count:: ideal 2570 lookaround 135
Was this dump made after you played with manual rate settings? If so,
please make a new one that only contains stats of what it tried with
automatic rate setting enabled.
- Felix
^ permalink raw reply
* about 802.11 scan and probe request
From: belle.shi @ 2009-10-26 2:32 UTC (permalink / raw)
To: linux-wireless
dear all,
is there anyone who read the standard "Part 11: Wireless LAN Medium
Access Control (MAC) and Physical Layer (PHY) Specifications" ?
and i spend two month to read the stardard, and i read a few code of
wpa_suppliant and
wpa_gui,there is one question: the scan have two mode:active or
passive,but when i run
the wpa_gui, there is only scan button, in the standard the scan
request is like
MLME-SCAN.request (
BSSType,
BSSID,
SSID,
ScanType,
ProbeDelay,
ChannelList,
MinChannelTime,
MaxChannelTime
)
but there are only three MAC frame formats:data frame, control frame
and Management
frame, and there is no scan frame, there is only a Probe Request frame,
so i am
stumped, what's the relationship between MLME-SCAN.request and Probe
Request frame, is
the MLME-SCAN.request and Probe Request frame only in different layer?
but the items is
also different, the MLME-SCAN.request have:(
BSSType, BSSID, SSID, ScanType, ProbeDelay, ChannelList,
MinChannelTime, MaxChannelTime), but the Probe Request frame body
only have two parts: SSID
and Supported rates. and in my view, i think the active scan is to
send Probe Request
frame, and the passive scan to receive the beacon frame, is it right?
thanks very much for advance!!
belle
^ permalink raw reply
* RE: [ath9k-devel] mac80211/ath9k/hostapd: Some clients unable to associate with AP
From: Joerg Pommnitz @ 2009-10-25 20:36 UTC (permalink / raw)
To: Jouni Malinen, Björn Smedman
Cc: Will Dyson, Johannes Berg, ath9k-devel, linux-wireless
In-Reply-To: <20091023163001.GA4911@jm.kir.nu>
I'll test tomorrow. Something is bothering me here: I have a current wireless-testing kernel
with ath5k and ath9 driver. I have traces that show that Win Vista successfully associates
with ath5k running in AP mode but fails with ath9k. How is this difference possible if the bug
is in the common code? Might there be another offsetting bug in ath5k?
--
Regards
Joerg
----- Ursprüngliche Mail ----
Von: Jouni Malinen <j@w1.fi>
An: Björn Smedman <bjorn.smedman@venatech.se>
CC: Joerg Pommnitz <pommnitz@yahoo.com>; Will Dyson <will.dyson@gmail.com>; Johannes Berg <johannes@sipsolutions.net>; ath9k-devel@venema.h4ckr.net; linux-wireless@vger.kernel.org
Gesendet: Freitag, den 23. Oktober 2009, 18:30:01 Uhr
Betreff: Re: [ath9k-devel] mac80211/ath9k/hostapd: Some clients unable to associate with AP
On Fri, Oct 23, 2009 at 05:27:27PM +0200, Björn Smedman wrote:
> It seems the problem is a typo in net/mac80211/tx.c that causes
> injected frames from hostapd not to be associated with the correct ap
> interface before going into ieee80211_tx_h_sequence(). This tiny patch
> solves my problems (and looks reasonable to me in any case):
Thanks! Would you be able to make the same patch against the
wireless-testing.git repository and add a Signed-off-by line to meet the
kernel submission requirements?
> diff -urN compat-wireless-2009-10-21-before_seqnum_fix/net/mac80211/tx.c
> compat-wireless-2009-10-21/net/mac80211/tx.c
> @@ -1445,7 +1445,7 @@
> if (tmp_sdata->vif.type != NL80211_IFTYPE_AP)
> continue;
> if (compare_ether_addr(tmp_sdata->dev->dev_addr,
> - hdr->addr2)) {
> + hdr->addr2) == 0) {
> dev_hold(tmp_sdata->dev);
> dev_put(sdata->dev);
> sdata = tmp_sdata;
This does indeed look like a typo. Though, I'm not sure how this would
have caused a regression between compat-wireless-2009-06-02 and
compat-wireless-2.6.32-rc1. The incorrect compare_ether_addr() use seems
to be there in the original commit that added this code
(25d834e16294c8dfd923dae6bdb8a055391a99a5 from September 12, 2008)..
Johannes: Any idea why the sequence number allocation for injected
frames from hostapd would have changed between 2009-06-02 and now? This
bug seems to be too old to explain that ;-).
--
Jouni Malinen PGP id EFC895FA
^ permalink raw reply
* Re: ath5k AP kernel panic when client uses SCP
From: Bob Copeland @ 2009-10-25 20:19 UTC (permalink / raw)
To: Tomasz Chmielewski
Cc: Gábor Stefanik, linux-wireless, linux-net, linux-mips
In-Reply-To: <4AE3431C.2000201@wpkg.org>
On Sat, Oct 24, 2009 at 2:10 PM, Tomasz Chmielewski <mangoo@wpkg.org> wrote:
> Bob Copeland wrote:
> Here is everything the system said after being powered on, including all
> page allocation failures and the final oops:
>
> http://www1.wpkg.org/skb_gso_segment/minicom.txt
>
> (and it looks slightly different than the last time).
In this case an order-0 allocation failed inside ieee80211_skb_resize,
which then called dev_release_skb() on the original skb. Off the top
of my head, it's unclear why the subsequent put_page would cause a fault.
This is a little out of my area so take it with a grain of salt :) but
in general order-0 allocation failures are bad news -- it couldn't get
a single free page, and that happened in under 3 minutes. Maybe poke
around in /proc/slabinfo to see where the memory went?
--
Bob Copeland %% www.bobcopeland.com
^ permalink raw reply
* Re: [PATCH] mac80211: fix for incorrect sequence number on hostapd injected frames
From: Johannes Berg @ 2009-10-25 18:59 UTC (permalink / raw)
To: Björn Smedman
Cc: linville, linux-wireless, Jouni Malinen, Joerg Pommnitz,
Will Dyson
In-Reply-To: <133e8d7e0910241155x4496b156p3c5d03450a71936a@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1713 bytes --]
On Sat, 2009-10-24 at 20:55 +0200, Björn Smedman wrote:
> When hostapd injects a frame, e.g. an authentication or association
> response, mac80211 looks for a suitable access point virtual interface
> to associate the frame with based on its source address. This makes it
> possible e.g. to correctly assign sequence numbers to the frames.
>
> A small typo in the ethernet address comparison statement caused a
> failure to find a suitable ap interface. Sequence numbers on such
> frames where therefore left unassigned causing some clients
> (especially windows-based 11b/g clients) to reject them and fail to
> authenticate or associate with the access point. This patch fixes the
> typo in the address comparison statement.
>
> Signed-off-by: Björn Smedman <bjorn.smedman@venatech.se>
Reviewed-by: Johannes Berg <johannes@sipsolutions.net>
and Cc: stable@kernel.org I think
> ---
> diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c
> index db4bda6..eaa4118 100644
> --- a/net/mac80211/tx.c
> +++ b/net/mac80211/tx.c
> @@ -1445,7 +1445,7 @@ static void ieee80211_xmit(struct
> ieee80211_sub_if_data *sdata,
> if (tmp_sdata->vif.type != NL80211_IFTYPE_AP)
> continue;
> if (compare_ether_addr(tmp_sdata->dev->dev_addr,
> - hdr->addr2)) {
> + hdr->addr2) == 0) {
> dev_hold(tmp_sdata->dev);
> dev_put(sdata->dev);
> sdata = tmp_sdata;
>
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^ permalink raw reply
* Rate-setting problem with Broadcom 4315
From: Larry Finger @ 2009-10-25 18:55 UTC (permalink / raw)
To: wireless
When my BCM4312 (ID 4315) runs in auto rate mode, the rate stays at
1Mb/s. If I manually set the rate, I see a tcpperf throughput ~1/2 the
rate that I set through a rate of 12 Mb/s. At 36 Mb/s, the rate is
best at 15.7 Mb/s. Why does mistrel not increase the rate?
The output of /sys/..../rc_stats is:
finger@larrylap:~> cat
/sys/kernel/debug/ieee80211/phy0/stations/00:14:bf:85:49:fa/rc_stats
rate throughput ewma prob this prob this succ/attempt
success attempts
1 0.9 99.1 100.0 0( 0) 3244
3282
2 1.8 95.7 100.0 0( 0) 12
12
5.5 4.8 95.7 100.0 0( 0) 12
12
11 9.2 96.8 100.0 0( 0) 12
12
P 6 5.6 99.9 100.0 0( 0) 58
58
9 8.0 95.7 100.0 0( 0) 11
11
12 10.6 95.7 100.0 0( 0) 12
12
18 15.7 96.6 100.0 0( 0) 14
15
24 20.3 95.7 100.0 0( 0) 11
11
36 29.0 95.4 94.5 0( 0) 1602
1670
T 48 38.7 99.2 100.0 1( 1) 32147
37752
t 54 32.9 75.9 100.0 0( 0) 8775
12788
Total packet count:: ideal 2570 lookaround 135
^ permalink raw reply
* Re: [PATCH] b43: LP-PHY: Begin implementing calibration & software RFKILL support
From: Michael Buesch @ 2009-10-25 16:00 UTC (permalink / raw)
To: Gábor Stefanik
Cc: John Linville, Larry Finger, Mark Huijgen, Broadcom Wireless,
linux-wireless
In-Reply-To: <69e28c910910250857l341cc114w46224b94cda36f3e@mail.gmail.com>
On Sunday 25 October 2009 16:57:44 Gábor Stefanik wrote:
> 2009/10/25 Michael Buesch <mb@bu3sch.de>:
> > On Sunday 25 October 2009 16:26:36 Gábor Stefanik wrote:
> >> Michael, could you please do the PHY reset part? I can't seem to
> >> understand its relationship to wireless_core_reset... also, it's
> >> heavily ssb-speak, which I am not good at.
> >
> > Where are the specifications?
> >
> > --
> > Greetings, Michael.
> >
>
> They are @ http://bcm-v4.sipsolutions.net/802.11/PHY/Reset - it shows
> some similarity to wireless_core_reset, but it is not an exact match.
Well, I don't know. Just implement it in another function.
I don't have the time to dig into this.
--
Greetings, Michael.
^ permalink raw reply
* Re: [PATCH] b43: LP-PHY: Begin implementing calibration & software RFKILL support
From: Gábor Stefanik @ 2009-10-25 15:57 UTC (permalink / raw)
To: Michael Buesch
Cc: John Linville, Larry Finger, Mark Huijgen, Broadcom Wireless,
linux-wireless
In-Reply-To: <200910251654.17050.mb@bu3sch.de>
2009/10/25 Michael Buesch <mb@bu3sch.de>:
> On Sunday 25 October 2009 16:26:36 Gábor Stefanik wrote:
>> Michael, could you please do the PHY reset part? I can't seem to
>> understand its relationship to wireless_core_reset... also, it's
>> heavily ssb-speak, which I am not good at.
>
> Where are the specifications?
>
> --
> Greetings, Michael.
>
They are @ http://bcm-v4.sipsolutions.net/802.11/PHY/Reset - it shows
some similarity to wireless_core_reset, but it is not an exact match.
--
Vista: [V]iruses, [I]ntruders, [S]pyware, [T]rojans and [A]dware. :-)
^ permalink raw reply
* Re: [PATCH] b43: LP-PHY: Begin implementing calibration & software RFKILL support
From: Michael Buesch @ 2009-10-25 15:54 UTC (permalink / raw)
To: Gábor Stefanik
Cc: John Linville, Larry Finger, Mark Huijgen, Broadcom Wireless,
linux-wireless
In-Reply-To: <1256484396-31063-1-git-send-email-netrolller.3d@gmail.com>
On Sunday 25 October 2009 16:26:36 Gábor Stefanik wrote:
> Michael, could you please do the PHY reset part? I can't seem to
> understand its relationship to wireless_core_reset... also, it's
> heavily ssb-speak, which I am not good at.
Where are the specifications?
--
Greetings, Michael.
^ permalink raw reply
* [PATCH] b43: LP-PHY: Begin implementing calibration & software RFKILL support
From: Gábor Stefanik @ 2009-10-25 15:26 UTC (permalink / raw)
To: John Linville, Michael Buesch, Larry Finger, Mark Huijgen
Cc: Broadcom Wireless, linux-wireless, Gábor Stefanik
This implements the following calibration functions:
-Set TX IQCC
-Set TX Power by Index
-PR41573 workaround (incomplete, needs PHY reset)
-Calc RX IQ Comp
-PHY Cordic
-Run Samples
-Start/Stop TX Tone
-part of PAPD Cal TX Power
-RX I/Q Calibration
-The basic structure of the periodic calibration wrapper
Software RFKILL (required by calibration) is also implemented in
this round.
Signed-off-by: Gábor Stefanik <netrolller.3d@gmail.com>
---
(Mail re-sent as my mailer seems to have dropped it; apologies if
you receive it twice.)
Michael, could you please do the PHY reset part? I can't seem to
understand its relationship to wireless_core_reset... also, it's
heavily ssb-speak, which I am not good at.
drivers/net/wireless/b43/phy_lp.c | 783 ++++++++++++++++++++++++++++++-------
drivers/net/wireless/b43/phy_lp.h | 11 +-
2 files changed, 658 insertions(+), 136 deletions(-)
diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index 07d9d03..9dcb39c 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -67,6 +67,7 @@ static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
struct b43_phy_lp *lpphy = phy->lp;
memset(lpphy, 0, sizeof(*lpphy));
+ lpphy->antenna = B43_ANTENNA_DEFAULT;
//TODO
}
@@ -379,8 +380,6 @@ static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
}
}
-/* lpphy_restore_dig_flt_state is unused but kept as a reference */
-#if 0
static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
{
static const u16 addr[] = {
@@ -401,7 +400,6 @@ static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
for (i = 0; i < ARRAY_SIZE(addr); i++)
b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
}
-#endif
static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
{
@@ -754,11 +752,17 @@ static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
}
}
+static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx)
+{
+ u16 trsw = (tx << 1) | rx;
+ b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+}
+
static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
{
lpphy_set_deaf(dev, user);
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+ lpphy_set_trsw_over(dev, false, true);
b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
@@ -793,6 +797,60 @@ static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
+static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
+{
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
+ if (dev->phy.rev >= 2) {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
+ b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
+ }
+ } else {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
+ }
+}
+
+static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
+{
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
+ if (dev->phy.rev >= 2) {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
+ b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
+ }
+ } else {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
+ }
+}
+
+static void lpphy_disable_tx_gain_override(struct b43_wldev *dev)
+{
+ if (dev->phy.rev < 2)
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
+ else {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF);
+ }
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF);
+}
+
+static void lpphy_enable_tx_gain_override(struct b43_wldev *dev)
+{
+ if (dev->phy.rev < 2)
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
+ else {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000);
+ }
+ b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40);
+}
+
static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
{
struct lpphy_tx_gains gains;
@@ -822,6 +880,17 @@ static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
}
+static u16 lpphy_get_pa_gain(struct b43_wldev *dev)
+{
+ return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F;
+}
+
+static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain)
+{
+ b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6);
+ b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8);
+}
+
static void lpphy_set_tx_gains(struct b43_wldev *dev,
struct lpphy_tx_gains gains)
{
@@ -832,25 +901,22 @@ static void lpphy_set_tx_gains(struct b43_wldev *dev,
b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
0xF800, rf_gain);
} else {
- pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
- pa_gain <<= 2;
+ pa_gain = lpphy_get_pa_gain(dev);
b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
(gains.pga << 8) | gains.gm);
+ /*
+ * SPEC FIXME The spec calls for (pa_gain << 8) here, but that
+ * conflicts with the spec for set_pa_gain! Vendor driver bug?
+ */
b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
- 0x8000, gains.pad | pa_gain);
+ 0x8000, gains.pad | (pa_gain << 6));
b43_phy_write(dev, B43_PHY_OFDM(0xFC),
(gains.pga << 8) | gains.gm);
b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
- 0x8000, gains.pad | pa_gain);
+ 0x8000, gains.pad | (pa_gain << 8));
}
lpphy_set_dac_gain(dev, gains.dac);
- if (dev->phy.rev < 2) {
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
- } else {
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
- }
- b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
+ lpphy_enable_tx_gain_override(dev);
}
static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
@@ -890,41 +956,6 @@ static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
}
}
-/* lpphy_disable_rx_gain_override is unused but kept as a reference */
-#if 0
-static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
-{
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
- if (dev->phy.rev >= 2) {
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
- b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
- }
- } else {
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
- }
-}
-#endif
-
-static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
-{
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
- if (dev->phy.rev >= 2) {
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
- b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
- }
- } else {
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
- }
-}
-
static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
{
if (dev->phy.rev < 2)
@@ -1009,8 +1040,7 @@ static int lpphy_loopback(struct b43_wldev *dev)
memset(&iq_est, 0, sizeof(iq_est));
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+ lpphy_set_trsw_over(dev, true, true);
b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
@@ -1132,7 +1162,7 @@ static void lpphy_set_tx_power_control(struct b43_wldev *dev,
b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
0x8FFF, ((u16)lpphy->tssi_npt << 16));
//TODO Set "TSSI Transmit Count" variable to total transmitted frame count
- //TODO Disable TX gain override
+ lpphy_disable_tx_gain_override(dev);
lpphy->tx_pwr_idx_over = -1;
}
}
@@ -1318,15 +1348,73 @@ static void lpphy_calibrate_rc(struct b43_wldev *dev)
}
}
+static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
+{
+ if (dev->phy.rev >= 2)
+ return; // rev2+ doesn't support antenna diversity
+
+ if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
+ return;
+
+ b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
+
+ b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
+ b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
+
+ b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
+
+ dev->phy.lp->antenna = antenna;
+}
+
+static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b)
+{
+ u16 tmp[2];
+
+ tmp[0] = a;
+ tmp[1] = b;
+ b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp);
+}
+
static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
{
struct b43_phy_lp *lpphy = dev->phy.lp;
+ struct lpphy_tx_gains gains;
+ u32 iq_comp, tx_gain, coeff, rf_power;
lpphy->tx_pwr_idx_over = index;
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
-
- //TODO
+ if (dev->phy.rev >= 2) {
+ iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320));
+ tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192));
+ gains.pad = (tx_gain >> 16) & 0xFF;
+ gains.gm = tx_gain & 0xFF;
+ gains.pga = (tx_gain >> 8) & 0xFF;
+ gains.dac = (iq_comp >> 28) & 0xFF;
+ lpphy_set_tx_gains(dev, gains);
+ } else {
+ iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320));
+ tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192));
+ b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
+ 0xF800, (tx_gain >> 4) & 0x7FFF);
+ lpphy_set_dac_gain(dev, tx_gain & 0x7);
+ lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F);
+ }
+ lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF);
+ lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF);
+ if (dev->phy.rev >= 2) {
+ coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448));
+ } else {
+ coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448));
+ }
+ b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF);
+ if (dev->phy.rev >= 2) {
+ rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576));
+ b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00,
+ rf_power & 0xFFFF);//SPEC FIXME mask & set != 0
+ }
+ lpphy_enable_tx_gain_override(dev);
}
static void lpphy_btcoex_override(struct b43_wldev *dev)
@@ -1335,58 +1423,45 @@ static void lpphy_btcoex_override(struct b43_wldev *dev)
b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
}
-static void lpphy_pr41573_workaround(struct b43_wldev *dev)
+static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
+ bool blocked)
{
- struct b43_phy_lp *lpphy = dev->phy.lp;
- u32 *saved_tab;
- const unsigned int saved_tab_size = 256;
- enum b43_lpphy_txpctl_mode txpctl_mode;
- s8 tx_pwr_idx_over;
- u16 tssi_npt, tssi_idx;
-
- saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
- if (!saved_tab) {
- b43err(dev->wl, "PR41573 failed. Out of memory!\n");
- return;
- }
-
- lpphy_read_tx_pctl_mode_from_hardware(dev);
- txpctl_mode = lpphy->txpctl_mode;
- tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
- tssi_npt = lpphy->tssi_npt;
- tssi_idx = lpphy->tssi_idx;
-
- if (dev->phy.rev < 2) {
- b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
- saved_tab_size, saved_tab);
+ //TODO check MAC control register
+ if (blocked) {
+ if (dev->phy.rev >= 2) {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
+ b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808);
+ } else {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018);
+ }
} else {
- b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
- saved_tab_size, saved_tab);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF);
+ if (dev->phy.rev >= 2)
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7);
+ else
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7);
}
- //TODO
-
- kfree(saved_tab);
}
-static void lpphy_calibration(struct b43_wldev *dev)
+/* This was previously called lpphy_japan_filter */
+static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
{
struct b43_phy_lp *lpphy = dev->phy.lp;
- enum b43_lpphy_txpctl_mode saved_pctl_mode;
-
- b43_mac_suspend(dev);
-
- lpphy_btcoex_override(dev);
- lpphy_read_tx_pctl_mode_from_hardware(dev);
- saved_pctl_mode = lpphy->txpctl_mode;
- lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
- //TODO Perform transmit power table I/Q LO calibration
- if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
- lpphy_pr41573_workaround(dev);
- //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
- lpphy_set_tx_power_control(dev, saved_pctl_mode);
- //TODO Perform I/Q calibration with a single control value set
+ u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
- b43_mac_enable(dev);
+ if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
+ b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
+ if ((dev->phy.rev == 1) && (lpphy->rc_cap))
+ lpphy_set_rc_cap(dev);
+ } else {
+ b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
+ }
}
static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
@@ -1495,6 +1570,473 @@ static void lpphy_tx_pctl_init(struct b43_wldev *dev)
}
}
+static void lpphy_pr41573_workaround(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ u32 *saved_tab;
+ const unsigned int saved_tab_size = 256;
+ enum b43_lpphy_txpctl_mode txpctl_mode;
+ s8 tx_pwr_idx_over;
+ u16 tssi_npt, tssi_idx;
+
+ saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
+ if (!saved_tab) {
+ b43err(dev->wl, "PR41573 failed. Out of memory!\n");
+ return;
+ }
+
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
+ txpctl_mode = lpphy->txpctl_mode;
+ tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
+ tssi_npt = lpphy->tssi_npt;
+ tssi_idx = lpphy->tssi_idx;
+
+ if (dev->phy.rev < 2) {
+ b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
+ saved_tab_size, saved_tab);
+ } else {
+ b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
+ saved_tab_size, saved_tab);
+ }
+ //FIXME PHY reset
+ lpphy_table_init(dev); //FIXME is table init needed?
+ lpphy_baseband_init(dev);
+ lpphy_tx_pctl_init(dev);
+ b43_lpphy_op_software_rfkill(dev, false);
+ lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+ if (dev->phy.rev < 2) {
+ b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0x140),
+ saved_tab_size, saved_tab);
+ } else {
+ b43_lptab_write_bulk(dev, B43_LPTAB32(7, 0x140),
+ saved_tab_size, saved_tab);
+ }
+ b43_write16(dev, B43_MMIO_CHANNEL, lpphy->channel);
+ lpphy->tssi_npt = tssi_npt;
+ lpphy->tssi_idx = tssi_idx;
+ lpphy_set_analog_filter(dev, lpphy->channel);
+ if (tx_pwr_idx_over != -1)
+ lpphy_set_tx_power_by_index(dev, tx_pwr_idx_over);
+ if (lpphy->rc_cap)
+ lpphy_set_rc_cap(dev);
+ b43_lpphy_op_set_rx_antenna(dev, lpphy->antenna);
+ lpphy_set_tx_power_control(dev, txpctl_mode);
+ kfree(saved_tab);
+}
+
+struct lpphy_rx_iq_comp { u8 chan; s8 c1, c0; };
+
+static const struct lpphy_rx_iq_comp lpphy_5354_iq_table[] = {
+ { .chan = 1, .c1 = -66, .c0 = 15, },
+ { .chan = 2, .c1 = -66, .c0 = 15, },
+ { .chan = 3, .c1 = -66, .c0 = 15, },
+ { .chan = 4, .c1 = -66, .c0 = 15, },
+ { .chan = 5, .c1 = -66, .c0 = 15, },
+ { .chan = 6, .c1 = -66, .c0 = 15, },
+ { .chan = 7, .c1 = -66, .c0 = 14, },
+ { .chan = 8, .c1 = -66, .c0 = 14, },
+ { .chan = 9, .c1 = -66, .c0 = 14, },
+ { .chan = 10, .c1 = -66, .c0 = 14, },
+ { .chan = 11, .c1 = -66, .c0 = 14, },
+ { .chan = 12, .c1 = -66, .c0 = 13, },
+ { .chan = 13, .c1 = -66, .c0 = 13, },
+ { .chan = 14, .c1 = -66, .c0 = 13, },
+};
+
+static const struct lpphy_rx_iq_comp lpphy_rev0_1_iq_table[] = {
+ { .chan = 1, .c1 = -64, .c0 = 13, },
+ { .chan = 2, .c1 = -64, .c0 = 13, },
+ { .chan = 3, .c1 = -64, .c0 = 13, },
+ { .chan = 4, .c1 = -64, .c0 = 13, },
+ { .chan = 5, .c1 = -64, .c0 = 12, },
+ { .chan = 6, .c1 = -64, .c0 = 12, },
+ { .chan = 7, .c1 = -64, .c0 = 12, },
+ { .chan = 8, .c1 = -64, .c0 = 12, },
+ { .chan = 9, .c1 = -64, .c0 = 12, },
+ { .chan = 10, .c1 = -64, .c0 = 11, },
+ { .chan = 11, .c1 = -64, .c0 = 11, },
+ { .chan = 12, .c1 = -64, .c0 = 11, },
+ { .chan = 13, .c1 = -64, .c0 = 11, },
+ { .chan = 14, .c1 = -64, .c0 = 10, },
+ { .chan = 34, .c1 = -62, .c0 = 24, },
+ { .chan = 38, .c1 = -62, .c0 = 24, },
+ { .chan = 42, .c1 = -62, .c0 = 24, },
+ { .chan = 46, .c1 = -62, .c0 = 23, },
+ { .chan = 36, .c1 = -62, .c0 = 24, },
+ { .chan = 40, .c1 = -62, .c0 = 24, },
+ { .chan = 44, .c1 = -62, .c0 = 23, },
+ { .chan = 48, .c1 = -62, .c0 = 23, },
+ { .chan = 52, .c1 = -62, .c0 = 23, },
+ { .chan = 56, .c1 = -62, .c0 = 22, },
+ { .chan = 60, .c1 = -62, .c0 = 22, },
+ { .chan = 64, .c1 = -62, .c0 = 22, },
+ { .chan = 100, .c1 = -62, .c0 = 16, },
+ { .chan = 104, .c1 = -62, .c0 = 16, },
+ { .chan = 108, .c1 = -62, .c0 = 15, },
+ { .chan = 112, .c1 = -62, .c0 = 14, },
+ { .chan = 116, .c1 = -62, .c0 = 14, },
+ { .chan = 120, .c1 = -62, .c0 = 13, },
+ { .chan = 124, .c1 = -62, .c0 = 12, },
+ { .chan = 128, .c1 = -62, .c0 = 12, },
+ { .chan = 132, .c1 = -62, .c0 = 12, },
+ { .chan = 136, .c1 = -62, .c0 = 11, },
+ { .chan = 140, .c1 = -62, .c0 = 10, },
+ { .chan = 149, .c1 = -61, .c0 = 9, },
+ { .chan = 153, .c1 = -61, .c0 = 9, },
+ { .chan = 157, .c1 = -61, .c0 = 9, },
+ { .chan = 161, .c1 = -61, .c0 = 8, },
+ { .chan = 165, .c1 = -61, .c0 = 8, },
+ { .chan = 184, .c1 = -62, .c0 = 25, },
+ { .chan = 188, .c1 = -62, .c0 = 25, },
+ { .chan = 192, .c1 = -62, .c0 = 25, },
+ { .chan = 196, .c1 = -62, .c0 = 25, },
+ { .chan = 200, .c1 = -62, .c0 = 25, },
+ { .chan = 204, .c1 = -62, .c0 = 25, },
+ { .chan = 208, .c1 = -62, .c0 = 25, },
+ { .chan = 212, .c1 = -62, .c0 = 25, },
+ { .chan = 216, .c1 = -62, .c0 = 26, },
+};
+
+static const struct lpphy_rx_iq_comp lpphy_rev2plus_iq_comp = {
+ .chan = 0,
+ .c1 = -64,
+ .c0 = 0,
+};
+
+static u8 lpphy_nbits(s32 val)
+{
+ u32 tmp = abs(val);
+ u8 nbits = 0;
+
+ while (tmp != 0) {
+ nbits++;
+ tmp >>= 1;
+ }
+
+ return nbits;
+}
+
+static int lpphy_calc_rx_iq_comp(struct b43_wldev *dev, u16 samples)
+{
+ struct lpphy_iq_est iq_est;
+ u16 c0, c1;
+ int prod, ipwr, qpwr, prod_msb, q_msb, tmp1, tmp2, tmp3, tmp4, ret;
+
+ c1 = b43_phy_read(dev, B43_LPPHY_RX_COMP_COEFF_S);
+ c0 = c1 >> 8;
+ c1 |= 0xFF;
+
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, 0x00C0);
+ b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF);
+
+ ret = lpphy_rx_iq_est(dev, samples, 32, &iq_est);
+ if (!ret)
+ goto out;
+
+ prod = iq_est.iq_prod;
+ ipwr = iq_est.i_pwr;
+ qpwr = iq_est.q_pwr;
+
+ if (ipwr + qpwr < 2) {
+ ret = 0;
+ goto out;
+ }
+
+ prod_msb = lpphy_nbits(prod);
+ q_msb = lpphy_nbits(qpwr);
+ tmp1 = prod_msb - 20;
+
+ if (tmp1 >= 0) {
+ tmp3 = ((prod << (30 - prod_msb)) + (ipwr >> (1 + tmp1))) /
+ (ipwr >> tmp1);
+ } else {
+ tmp3 = ((prod << (30 - prod_msb)) + (ipwr << (-1 - tmp1))) /
+ (ipwr << -tmp1);
+ }
+
+ tmp2 = q_msb - 11;
+
+ if (tmp2 >= 0)
+ tmp4 = (qpwr << (31 - q_msb)) / (ipwr >> tmp2);
+ else
+ tmp4 = (qpwr << (31 - q_msb)) / (ipwr << -tmp2);
+
+ tmp4 -= tmp3 * tmp3;
+ tmp4 = -int_sqrt(tmp4);
+
+ c0 = tmp3 >> 3;
+ c1 = tmp4 >> 4;
+
+out:
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, c1);
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF, c0 << 8);
+ return ret;
+}
+
+/* Complex number using 2 32-bit signed integers */
+typedef struct {s32 i, q;} lpphy_c32;
+
+static lpphy_c32 lpphy_cordic(int theta)
+{
+ u32 arctg[] = { 2949120, 1740967, 919879, 466945, 234379, 117304,
+ 58666, 29335, 14668, 7334, 3667, 1833, 917, 458,
+ 229, 115, 57, 29, };
+ int i, tmp, signx = 1, angle = 0;
+ lpphy_c32 ret = { .i = 39797, .q = 0, };
+
+ theta = clamp_t(int, theta, -180, 180);
+
+ if (theta > 90) {
+ theta -= 180;
+ signx = -1;
+ } else if (theta < -90) {
+ theta += 180;
+ signx = -1;
+ }
+
+ for (i = 0; i <= 17; i++) {
+ if (theta > angle) {
+ tmp = ret.i - (ret.q >> i);
+ ret.q += ret.i >> i;
+ ret.i = tmp;
+ angle += arctg[i];
+ } else {
+ tmp = ret.i + (ret.q >> i);
+ ret.q -= ret.i >> i;
+ ret.i = tmp;
+ angle -= arctg[i];
+ }
+ }
+
+ ret.i *= signx;
+ ret.q *= signx;
+
+ return ret;
+}
+
+static void lpphy_run_samples(struct b43_wldev *dev, u16 samples, u16 loops,
+ u16 wait)
+{
+ b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL,
+ 0xFFC0, samples - 1);
+ if (loops != 0xFFFF)
+ loops--;
+ b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000, loops);
+ b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, 0x3F, wait << 6);
+ b43_phy_set(dev, B43_LPPHY_A_PHY_CTL_ADDR, 0x1);
+}
+
+//SPEC FIXME what does a negative freq mean?
+static void lpphy_start_tx_tone(struct b43_wldev *dev, s32 freq, u16 max)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ u16 buf[64];
+ int i, samples = 0, angle = 0, rotation = (9 * freq) / 500;
+ lpphy_c32 sample;
+
+ lpphy->tx_tone_freq = freq;
+
+ if (freq) {
+ /* Find i for which abs(freq) integrally divides 20000 * i */
+ for (i = 1; samples * abs(freq) != 20000 * i; i++) {
+ samples = (20000 * i) / abs(freq);
+ if(B43_WARN_ON(samples > 63))
+ return;
+ }
+ } else {
+ samples = 2;
+ }
+
+ for (i = 0; i < samples; i++) {
+ sample = lpphy_cordic(angle);
+ angle += rotation;
+ buf[i] = ((sample.i * max) & 0xFF) << 8;
+ buf[i] |= (sample.q * max) & 0xFF;
+ }
+
+ b43_lptab_write_bulk(dev, B43_LPTAB16(5, 0), samples, buf);
+
+ lpphy_run_samples(dev, samples, 0xFFFF, 0);
+}
+
+static void lpphy_stop_tx_tone(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ int i;
+
+ lpphy->tx_tone_freq = 0;
+
+ b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000);
+ for (i = 0; i < 31; i++) {
+ if (!(b43_phy_read(dev, B43_LPPHY_A_PHY_CTL_ADDR) & 0x1))
+ break;
+ udelay(100);
+ }
+}
+
+
+static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains,
+ int mode, bool useindex, u8 index)
+{
+ //TODO
+}
+
+static void lpphy_papd_cal_txpwr(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ struct ssb_bus *bus = dev->dev->bus;
+ struct lpphy_tx_gains gains, oldgains;
+ int old_txpctl, old_afe_ovr, old_rf, old_bbmult;
+
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
+ old_txpctl = lpphy->txpctl_mode;
+ old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
+ if (old_afe_ovr)
+ oldgains = lpphy_get_tx_gains(dev);
+ old_rf = b43_phy_read(dev, B43_LPPHY_RF_PWR_OVERRIDE) & 0xFF;
+ old_bbmult = lpphy_get_bb_mult(dev);
+
+ lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+
+ if (bus->chip_id == 0x4325 && bus->chip_rev == 0)
+ lpphy_papd_cal(dev, gains, 0, 1, 30);
+ else
+ lpphy_papd_cal(dev, gains, 0, 1, 65);
+
+ if (old_afe_ovr)
+ lpphy_set_tx_gains(dev, oldgains);
+ lpphy_set_bb_mult(dev, old_bbmult);
+ lpphy_set_tx_power_control(dev, old_txpctl);
+ b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, old_rf);
+}
+
+static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx,
+ bool rx, bool pa, struct lpphy_tx_gains *gains)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ struct ssb_bus *bus = dev->dev->bus;
+ const struct lpphy_rx_iq_comp *iqcomp = NULL;
+ struct lpphy_tx_gains nogains, oldgains;
+ u16 tmp;
+ int i, ret;
+
+ memset(&nogains, 0, sizeof(nogains));
+ memset(&oldgains, 0, sizeof(oldgains));
+
+ if (bus->chip_id == 0x5354) {
+ for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) {
+ if (lpphy_5354_iq_table[i].chan == lpphy->channel) {
+ iqcomp = &lpphy_5354_iq_table[i];
+ }
+ }
+ } else if (dev->phy.rev >= 2) {
+ iqcomp = &lpphy_rev2plus_iq_comp;
+ } else {
+ for (i = 0; i < ARRAY_SIZE(lpphy_rev0_1_iq_table); i++) {
+ if (lpphy_rev0_1_iq_table[i].chan == lpphy->channel) {
+ iqcomp = &lpphy_rev0_1_iq_table[i];
+ }
+ }
+ }
+
+ if (B43_WARN_ON(!iqcomp))
+ return 0;
+
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, iqcomp->c1);
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S,
+ 0x00FF, iqcomp->c0 << 8);
+
+ if (noise) {
+ tx = true;
+ rx = false;
+ pa = false;
+ }
+
+ lpphy_set_trsw_over(dev, tx, rx);
+
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
+ b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
+ 0xFFF7, pa << 3);
+ } else {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
+ b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
+ 0xFFDF, pa << 5);
+ }
+
+ tmp = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
+
+ if (noise)
+ lpphy_set_rx_gain(dev, 0x2D5D);
+ else {
+ if (tmp)
+ oldgains = lpphy_get_tx_gains(dev);
+ if (!gains)
+ gains = &nogains;
+ lpphy_set_tx_gains(dev, *gains);
+ }
+
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
+ lpphy_set_deaf(dev, false);
+ if (noise)
+ ret = lpphy_calc_rx_iq_comp(dev, 0xFFF0);
+ else {
+ lpphy_start_tx_tone(dev, 4000, 100);
+ ret = lpphy_calc_rx_iq_comp(dev, 0x4000);
+ lpphy_stop_tx_tone(dev);
+ }
+ lpphy_clear_deaf(dev, false);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF);
+ if (!noise) {
+ if (tmp)
+ lpphy_set_tx_gains(dev, oldgains);
+ else
+ lpphy_disable_tx_gain_override(dev);
+ }
+ lpphy_disable_rx_gain_override(dev);
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF);
+ return ret;
+}
+
+static void lpphy_calibration(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ enum b43_lpphy_txpctl_mode saved_pctl_mode;
+ bool full_cal = false;
+
+ if (lpphy->full_calib_chan != lpphy->channel) {
+ full_cal = true;
+ lpphy->full_calib_chan = lpphy->channel;
+ }
+
+ b43_mac_suspend(dev);
+
+ lpphy_btcoex_override(dev);
+ if (dev->phy.rev >= 2)
+ lpphy_save_dig_flt_state(dev);
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
+ saved_pctl_mode = lpphy->txpctl_mode;
+ lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+ //TODO Perform transmit power table I/Q LO calibration
+ if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
+ lpphy_pr41573_workaround(dev);
+ if ((dev->phy.rev >= 2) && full_cal) {
+ lpphy_papd_cal_txpwr(dev);
+ }
+ lpphy_set_tx_power_control(dev, saved_pctl_mode);
+ if (dev->phy.rev >= 2)
+ lpphy_restore_dig_flt_state(dev);
+ lpphy_rx_iq_cal(dev, true, true, false, false, NULL);
+
+ b43_mac_enable(dev);
+}
+
static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
@@ -1539,12 +2081,6 @@ static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}
-static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
- bool blocked)
-{
- //TODO
-}
-
struct b206x_channel {
u8 channel;
u16 freq;
@@ -2010,22 +2546,6 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
return err;
}
-
-/* This was previously called lpphy_japan_filter */
-static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
-{
- struct b43_phy_lp *lpphy = dev->phy.lp;
- u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
-
- if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
- b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
- if ((dev->phy.rev == 1) && (lpphy->rc_cap))
- lpphy_set_rc_cap(dev);
- } else {
- b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
- }
-}
-
static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
{
u16 tmp;
@@ -2210,18 +2730,6 @@ static int b43_lpphy_op_init(struct b43_wldev *dev)
return 0;
}
-static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
-{
- if (dev->phy.rev >= 2)
- return; // rev2+ doesn't support antenna diversity
-
- if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
- return;
-
- b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
- b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
-}
-
static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
{
//TODO
@@ -2244,6 +2752,11 @@ void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on)
}
}
+static void b43_lpphy_op_pwork_15sec(struct b43_wldev *dev)
+{
+ //TODO
+}
+
const struct b43_phy_operations b43_phyops_lp = {
.allocate = b43_lpphy_op_allocate,
.free = b43_lpphy_op_free,
@@ -2261,4 +2774,6 @@ const struct b43_phy_operations b43_phyops_lp = {
.set_rx_antenna = b43_lpphy_op_set_rx_antenna,
.recalc_txpower = b43_lpphy_op_recalc_txpower,
.adjust_txpower = b43_lpphy_op_adjust_txpower,
+ .pwork_15sec = b43_lpphy_op_pwork_15sec,
+ .pwork_60sec = lpphy_calibration,
};
diff --git a/drivers/net/wireless/b43/phy_lp.h b/drivers/net/wireless/b43/phy_lp.h
index c3232c1..62737f7 100644
--- a/drivers/net/wireless/b43/phy_lp.h
+++ b/drivers/net/wireless/b43/phy_lp.h
@@ -286,6 +286,7 @@
#define B43_LPPHY_TR_LOOKUP_6 B43_PHY_OFDM(0xC8) /* TR Lookup 6 */
#define B43_LPPHY_TR_LOOKUP_7 B43_PHY_OFDM(0xC9) /* TR Lookup 7 */
#define B43_LPPHY_TR_LOOKUP_8 B43_PHY_OFDM(0xCA) /* TR Lookup 8 */
+#define B43_LPPHY_RF_PWR_OVERRIDE B43_PHY_OFDM(0xD3) /* RF power override */
@@ -871,12 +872,12 @@ struct b43_phy_lp {
u8 rssi_gs;
/* RC cap */
- u8 rc_cap; /* FIXME initial value? */
+ u8 rc_cap;
/* BX arch */
u8 bx_arch;
/* Full calibration channel */
- u8 full_calib_chan; /* FIXME initial value? */
+ u8 full_calib_chan;
/* Transmit iqlocal best coeffs */
bool tx_iqloc_best_coeffs_valid;
@@ -891,6 +892,12 @@ struct b43_phy_lp {
/* The channel we are tuned to */
u8 channel;
+
+ /* The active antenna diversity mode */
+ int antenna;
+
+ /* Frequency of the active TX tone */
+ int tx_tone_freq;
};
enum tssi_mux_mode {
--
1.6.4.2
^ permalink raw reply related
* [PATCH] b43: LP-PHY: Begin implementing calibration & software RFKILL support
From: Gábor Stefanik @ 2009-10-25 15:22 UTC (permalink / raw)
To: John Linville, Michael Buesch, Larry Finger, Mark Huijgen
Cc: Broadcom Wireless, linux-wireless
This implements the following calibration functions:
-Set TX IQCC
-Set TX Power by Index
-PR41573 workaround (incomplete, needs PHY reset)
-Calc RX IQ Comp
-PHY Cordic
-Run Samples
-Start/Stop TX Tone
-part of PAPD Cal TX Power
-RX I/Q Calibration
-The basic structure of the periodic calibration wrapper
Software RFKILL (required by calibration) is also implemented in
this round.
Signed-off-by: Gábor Stefanik <netrolller.3d@gmail.com>
---
Michael, could you please do the PHY reset part? I can't seem to
understand its relationship to wireless_core_reset... also, it's
heavily ssb-speak, which I am not good at.
drivers/net/wireless/b43/phy_lp.c | 783 ++++++++++++++++++++++++++++++-------
drivers/net/wireless/b43/phy_lp.h | 11 +-
2 files changed, 658 insertions(+), 136 deletions(-)
diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index 07d9d03..9dcb39c 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -67,6 +67,7 @@ static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
struct b43_phy_lp *lpphy = phy->lp;
memset(lpphy, 0, sizeof(*lpphy));
+ lpphy->antenna = B43_ANTENNA_DEFAULT;
//TODO
}
@@ -379,8 +380,6 @@ static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
}
}
-/* lpphy_restore_dig_flt_state is unused but kept as a reference */
-#if 0
static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
{
static const u16 addr[] = {
@@ -401,7 +400,6 @@ static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
for (i = 0; i < ARRAY_SIZE(addr); i++)
b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
}
-#endif
static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
{
@@ -754,11 +752,17 @@ static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
}
}
+static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx)
+{
+ u16 trsw = (tx << 1) | rx;
+ b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+}
+
static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
{
lpphy_set_deaf(dev, user);
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+ lpphy_set_trsw_over(dev, false, true);
b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
@@ -793,6 +797,60 @@ static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
+static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
+{
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
+ if (dev->phy.rev >= 2) {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
+ b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
+ }
+ } else {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
+ }
+}
+
+static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
+{
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
+ if (dev->phy.rev >= 2) {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
+ b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
+ }
+ } else {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
+ }
+}
+
+static void lpphy_disable_tx_gain_override(struct b43_wldev *dev)
+{
+ if (dev->phy.rev < 2)
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
+ else {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF);
+ }
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF);
+}
+
+static void lpphy_enable_tx_gain_override(struct b43_wldev *dev)
+{
+ if (dev->phy.rev < 2)
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
+ else {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000);
+ }
+ b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40);
+}
+
static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
{
struct lpphy_tx_gains gains;
@@ -822,6 +880,17 @@ static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
}
+static u16 lpphy_get_pa_gain(struct b43_wldev *dev)
+{
+ return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F;
+}
+
+static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain)
+{
+ b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6);
+ b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8);
+}
+
static void lpphy_set_tx_gains(struct b43_wldev *dev,
struct lpphy_tx_gains gains)
{
@@ -832,25 +901,22 @@ static void lpphy_set_tx_gains(struct b43_wldev *dev,
b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
0xF800, rf_gain);
} else {
- pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
- pa_gain <<= 2;
+ pa_gain = lpphy_get_pa_gain(dev);
b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
(gains.pga << 8) | gains.gm);
+ /*
+ * SPEC FIXME The spec calls for (pa_gain << 8) here, but that
+ * conflicts with the spec for set_pa_gain! Vendor driver bug?
+ */
b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
- 0x8000, gains.pad | pa_gain);
+ 0x8000, gains.pad | (pa_gain << 6));
b43_phy_write(dev, B43_PHY_OFDM(0xFC),
(gains.pga << 8) | gains.gm);
b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
- 0x8000, gains.pad | pa_gain);
+ 0x8000, gains.pad | (pa_gain << 8));
}
lpphy_set_dac_gain(dev, gains.dac);
- if (dev->phy.rev < 2) {
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
- } else {
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
- }
- b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
+ lpphy_enable_tx_gain_override(dev);
}
static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
@@ -890,41 +956,6 @@ static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
}
}
-/* lpphy_disable_rx_gain_override is unused but kept as a reference */
-#if 0
-static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
-{
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
- if (dev->phy.rev >= 2) {
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
- b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
- }
- } else {
- b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
- }
-}
-#endif
-
-static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
-{
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
- if (dev->phy.rev >= 2) {
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
- b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
- }
- } else {
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
- }
-}
-
static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
{
if (dev->phy.rev < 2)
@@ -1009,8 +1040,7 @@ static int lpphy_loopback(struct b43_wldev *dev)
memset(&iq_est, 0, sizeof(iq_est));
- b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
- b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+ lpphy_set_trsw_over(dev, true, true);
b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
@@ -1132,7 +1162,7 @@ static void lpphy_set_tx_power_control(struct b43_wldev *dev,
b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
0x8FFF, ((u16)lpphy->tssi_npt << 16));
//TODO Set "TSSI Transmit Count" variable to total transmitted frame count
- //TODO Disable TX gain override
+ lpphy_disable_tx_gain_override(dev);
lpphy->tx_pwr_idx_over = -1;
}
}
@@ -1318,15 +1348,73 @@ static void lpphy_calibrate_rc(struct b43_wldev *dev)
}
}
+static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
+{
+ if (dev->phy.rev >= 2)
+ return; // rev2+ doesn't support antenna diversity
+
+ if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
+ return;
+
+ b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
+
+ b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
+ b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
+
+ b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
+
+ dev->phy.lp->antenna = antenna;
+}
+
+static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b)
+{
+ u16 tmp[2];
+
+ tmp[0] = a;
+ tmp[1] = b;
+ b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp);
+}
+
static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
{
struct b43_phy_lp *lpphy = dev->phy.lp;
+ struct lpphy_tx_gains gains;
+ u32 iq_comp, tx_gain, coeff, rf_power;
lpphy->tx_pwr_idx_over = index;
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
-
- //TODO
+ if (dev->phy.rev >= 2) {
+ iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320));
+ tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192));
+ gains.pad = (tx_gain >> 16) & 0xFF;
+ gains.gm = tx_gain & 0xFF;
+ gains.pga = (tx_gain >> 8) & 0xFF;
+ gains.dac = (iq_comp >> 28) & 0xFF;
+ lpphy_set_tx_gains(dev, gains);
+ } else {
+ iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320));
+ tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192));
+ b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
+ 0xF800, (tx_gain >> 4) & 0x7FFF);
+ lpphy_set_dac_gain(dev, tx_gain & 0x7);
+ lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F);
+ }
+ lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF);
+ lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF);
+ if (dev->phy.rev >= 2) {
+ coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448));
+ } else {
+ coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448));
+ }
+ b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF);
+ if (dev->phy.rev >= 2) {
+ rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576));
+ b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00,
+ rf_power & 0xFFFF);//SPEC FIXME mask & set != 0
+ }
+ lpphy_enable_tx_gain_override(dev);
}
static void lpphy_btcoex_override(struct b43_wldev *dev)
@@ -1335,58 +1423,45 @@ static void lpphy_btcoex_override(struct b43_wldev *dev)
b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
}
-static void lpphy_pr41573_workaround(struct b43_wldev *dev)
+static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
+ bool blocked)
{
- struct b43_phy_lp *lpphy = dev->phy.lp;
- u32 *saved_tab;
- const unsigned int saved_tab_size = 256;
- enum b43_lpphy_txpctl_mode txpctl_mode;
- s8 tx_pwr_idx_over;
- u16 tssi_npt, tssi_idx;
-
- saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
- if (!saved_tab) {
- b43err(dev->wl, "PR41573 failed. Out of memory!\n");
- return;
- }
-
- lpphy_read_tx_pctl_mode_from_hardware(dev);
- txpctl_mode = lpphy->txpctl_mode;
- tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
- tssi_npt = lpphy->tssi_npt;
- tssi_idx = lpphy->tssi_idx;
-
- if (dev->phy.rev < 2) {
- b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
- saved_tab_size, saved_tab);
+ //TODO check MAC control register
+ if (blocked) {
+ if (dev->phy.rev >= 2) {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
+ b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808);
+ } else {
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018);
+ }
} else {
- b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
- saved_tab_size, saved_tab);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF);
+ if (dev->phy.rev >= 2)
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7);
+ else
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7);
}
- //TODO
-
- kfree(saved_tab);
}
-static void lpphy_calibration(struct b43_wldev *dev)
+/* This was previously called lpphy_japan_filter */
+static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
{
struct b43_phy_lp *lpphy = dev->phy.lp;
- enum b43_lpphy_txpctl_mode saved_pctl_mode;
-
- b43_mac_suspend(dev);
-
- lpphy_btcoex_override(dev);
- lpphy_read_tx_pctl_mode_from_hardware(dev);
- saved_pctl_mode = lpphy->txpctl_mode;
- lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
- //TODO Perform transmit power table I/Q LO calibration
- if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
- lpphy_pr41573_workaround(dev);
- //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
- lpphy_set_tx_power_control(dev, saved_pctl_mode);
- //TODO Perform I/Q calibration with a single control value set
+ u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
- b43_mac_enable(dev);
+ if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
+ b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
+ if ((dev->phy.rev == 1) && (lpphy->rc_cap))
+ lpphy_set_rc_cap(dev);
+ } else {
+ b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
+ }
}
static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
@@ -1495,6 +1570,473 @@ static void lpphy_tx_pctl_init(struct b43_wldev *dev)
}
}
+static void lpphy_pr41573_workaround(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ u32 *saved_tab;
+ const unsigned int saved_tab_size = 256;
+ enum b43_lpphy_txpctl_mode txpctl_mode;
+ s8 tx_pwr_idx_over;
+ u16 tssi_npt, tssi_idx;
+
+ saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
+ if (!saved_tab) {
+ b43err(dev->wl, "PR41573 failed. Out of memory!\n");
+ return;
+ }
+
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
+ txpctl_mode = lpphy->txpctl_mode;
+ tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
+ tssi_npt = lpphy->tssi_npt;
+ tssi_idx = lpphy->tssi_idx;
+
+ if (dev->phy.rev < 2) {
+ b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
+ saved_tab_size, saved_tab);
+ } else {
+ b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
+ saved_tab_size, saved_tab);
+ }
+ //FIXME PHY reset
+ lpphy_table_init(dev); //FIXME is table init needed?
+ lpphy_baseband_init(dev);
+ lpphy_tx_pctl_init(dev);
+ b43_lpphy_op_software_rfkill(dev, false);
+ lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+ if (dev->phy.rev < 2) {
+ b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0x140),
+ saved_tab_size, saved_tab);
+ } else {
+ b43_lptab_write_bulk(dev, B43_LPTAB32(7, 0x140),
+ saved_tab_size, saved_tab);
+ }
+ b43_write16(dev, B43_MMIO_CHANNEL, lpphy->channel);
+ lpphy->tssi_npt = tssi_npt;
+ lpphy->tssi_idx = tssi_idx;
+ lpphy_set_analog_filter(dev, lpphy->channel);
+ if (tx_pwr_idx_over != -1)
+ lpphy_set_tx_power_by_index(dev, tx_pwr_idx_over);
+ if (lpphy->rc_cap)
+ lpphy_set_rc_cap(dev);
+ b43_lpphy_op_set_rx_antenna(dev, lpphy->antenna);
+ lpphy_set_tx_power_control(dev, txpctl_mode);
+ kfree(saved_tab);
+}
+
+struct lpphy_rx_iq_comp { u8 chan; s8 c1, c0; };
+
+static const struct lpphy_rx_iq_comp lpphy_5354_iq_table[] = {
+ { .chan = 1, .c1 = -66, .c0 = 15, },
+ { .chan = 2, .c1 = -66, .c0 = 15, },
+ { .chan = 3, .c1 = -66, .c0 = 15, },
+ { .chan = 4, .c1 = -66, .c0 = 15, },
+ { .chan = 5, .c1 = -66, .c0 = 15, },
+ { .chan = 6, .c1 = -66, .c0 = 15, },
+ { .chan = 7, .c1 = -66, .c0 = 14, },
+ { .chan = 8, .c1 = -66, .c0 = 14, },
+ { .chan = 9, .c1 = -66, .c0 = 14, },
+ { .chan = 10, .c1 = -66, .c0 = 14, },
+ { .chan = 11, .c1 = -66, .c0 = 14, },
+ { .chan = 12, .c1 = -66, .c0 = 13, },
+ { .chan = 13, .c1 = -66, .c0 = 13, },
+ { .chan = 14, .c1 = -66, .c0 = 13, },
+};
+
+static const struct lpphy_rx_iq_comp lpphy_rev0_1_iq_table[] = {
+ { .chan = 1, .c1 = -64, .c0 = 13, },
+ { .chan = 2, .c1 = -64, .c0 = 13, },
+ { .chan = 3, .c1 = -64, .c0 = 13, },
+ { .chan = 4, .c1 = -64, .c0 = 13, },
+ { .chan = 5, .c1 = -64, .c0 = 12, },
+ { .chan = 6, .c1 = -64, .c0 = 12, },
+ { .chan = 7, .c1 = -64, .c0 = 12, },
+ { .chan = 8, .c1 = -64, .c0 = 12, },
+ { .chan = 9, .c1 = -64, .c0 = 12, },
+ { .chan = 10, .c1 = -64, .c0 = 11, },
+ { .chan = 11, .c1 = -64, .c0 = 11, },
+ { .chan = 12, .c1 = -64, .c0 = 11, },
+ { .chan = 13, .c1 = -64, .c0 = 11, },
+ { .chan = 14, .c1 = -64, .c0 = 10, },
+ { .chan = 34, .c1 = -62, .c0 = 24, },
+ { .chan = 38, .c1 = -62, .c0 = 24, },
+ { .chan = 42, .c1 = -62, .c0 = 24, },
+ { .chan = 46, .c1 = -62, .c0 = 23, },
+ { .chan = 36, .c1 = -62, .c0 = 24, },
+ { .chan = 40, .c1 = -62, .c0 = 24, },
+ { .chan = 44, .c1 = -62, .c0 = 23, },
+ { .chan = 48, .c1 = -62, .c0 = 23, },
+ { .chan = 52, .c1 = -62, .c0 = 23, },
+ { .chan = 56, .c1 = -62, .c0 = 22, },
+ { .chan = 60, .c1 = -62, .c0 = 22, },
+ { .chan = 64, .c1 = -62, .c0 = 22, },
+ { .chan = 100, .c1 = -62, .c0 = 16, },
+ { .chan = 104, .c1 = -62, .c0 = 16, },
+ { .chan = 108, .c1 = -62, .c0 = 15, },
+ { .chan = 112, .c1 = -62, .c0 = 14, },
+ { .chan = 116, .c1 = -62, .c0 = 14, },
+ { .chan = 120, .c1 = -62, .c0 = 13, },
+ { .chan = 124, .c1 = -62, .c0 = 12, },
+ { .chan = 128, .c1 = -62, .c0 = 12, },
+ { .chan = 132, .c1 = -62, .c0 = 12, },
+ { .chan = 136, .c1 = -62, .c0 = 11, },
+ { .chan = 140, .c1 = -62, .c0 = 10, },
+ { .chan = 149, .c1 = -61, .c0 = 9, },
+ { .chan = 153, .c1 = -61, .c0 = 9, },
+ { .chan = 157, .c1 = -61, .c0 = 9, },
+ { .chan = 161, .c1 = -61, .c0 = 8, },
+ { .chan = 165, .c1 = -61, .c0 = 8, },
+ { .chan = 184, .c1 = -62, .c0 = 25, },
+ { .chan = 188, .c1 = -62, .c0 = 25, },
+ { .chan = 192, .c1 = -62, .c0 = 25, },
+ { .chan = 196, .c1 = -62, .c0 = 25, },
+ { .chan = 200, .c1 = -62, .c0 = 25, },
+ { .chan = 204, .c1 = -62, .c0 = 25, },
+ { .chan = 208, .c1 = -62, .c0 = 25, },
+ { .chan = 212, .c1 = -62, .c0 = 25, },
+ { .chan = 216, .c1 = -62, .c0 = 26, },
+};
+
+static const struct lpphy_rx_iq_comp lpphy_rev2plus_iq_comp = {
+ .chan = 0,
+ .c1 = -64,
+ .c0 = 0,
+};
+
+static u8 lpphy_nbits(s32 val)
+{
+ u32 tmp = abs(val);
+ u8 nbits = 0;
+
+ while (tmp != 0) {
+ nbits++;
+ tmp >>= 1;
+ }
+
+ return nbits;
+}
+
+static int lpphy_calc_rx_iq_comp(struct b43_wldev *dev, u16 samples)
+{
+ struct lpphy_iq_est iq_est;
+ u16 c0, c1;
+ int prod, ipwr, qpwr, prod_msb, q_msb, tmp1, tmp2, tmp3, tmp4, ret;
+
+ c1 = b43_phy_read(dev, B43_LPPHY_RX_COMP_COEFF_S);
+ c0 = c1 >> 8;
+ c1 |= 0xFF;
+
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, 0x00C0);
+ b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF);
+
+ ret = lpphy_rx_iq_est(dev, samples, 32, &iq_est);
+ if (!ret)
+ goto out;
+
+ prod = iq_est.iq_prod;
+ ipwr = iq_est.i_pwr;
+ qpwr = iq_est.q_pwr;
+
+ if (ipwr + qpwr < 2) {
+ ret = 0;
+ goto out;
+ }
+
+ prod_msb = lpphy_nbits(prod);
+ q_msb = lpphy_nbits(qpwr);
+ tmp1 = prod_msb - 20;
+
+ if (tmp1 >= 0) {
+ tmp3 = ((prod << (30 - prod_msb)) + (ipwr >> (1 + tmp1))) /
+ (ipwr >> tmp1);
+ } else {
+ tmp3 = ((prod << (30 - prod_msb)) + (ipwr << (-1 - tmp1))) /
+ (ipwr << -tmp1);
+ }
+
+ tmp2 = q_msb - 11;
+
+ if (tmp2 >= 0)
+ tmp4 = (qpwr << (31 - q_msb)) / (ipwr >> tmp2);
+ else
+ tmp4 = (qpwr << (31 - q_msb)) / (ipwr << -tmp2);
+
+ tmp4 -= tmp3 * tmp3;
+ tmp4 = -int_sqrt(tmp4);
+
+ c0 = tmp3 >> 3;
+ c1 = tmp4 >> 4;
+
+out:
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, c1);
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF, c0 << 8);
+ return ret;
+}
+
+/* Complex number using 2 32-bit signed integers */
+typedef struct {s32 i, q;} lpphy_c32;
+
+static lpphy_c32 lpphy_cordic(int theta)
+{
+ u32 arctg[] = { 2949120, 1740967, 919879, 466945, 234379, 117304,
+ 58666, 29335, 14668, 7334, 3667, 1833, 917, 458,
+ 229, 115, 57, 29, };
+ int i, tmp, signx = 1, angle = 0;
+ lpphy_c32 ret = { .i = 39797, .q = 0, };
+
+ theta = clamp_t(int, theta, -180, 180);
+
+ if (theta > 90) {
+ theta -= 180;
+ signx = -1;
+ } else if (theta < -90) {
+ theta += 180;
+ signx = -1;
+ }
+
+ for (i = 0; i <= 17; i++) {
+ if (theta > angle) {
+ tmp = ret.i - (ret.q >> i);
+ ret.q += ret.i >> i;
+ ret.i = tmp;
+ angle += arctg[i];
+ } else {
+ tmp = ret.i + (ret.q >> i);
+ ret.q -= ret.i >> i;
+ ret.i = tmp;
+ angle -= arctg[i];
+ }
+ }
+
+ ret.i *= signx;
+ ret.q *= signx;
+
+ return ret;
+}
+
+static void lpphy_run_samples(struct b43_wldev *dev, u16 samples, u16 loops,
+ u16 wait)
+{
+ b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL,
+ 0xFFC0, samples - 1);
+ if (loops != 0xFFFF)
+ loops--;
+ b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000, loops);
+ b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, 0x3F, wait << 6);
+ b43_phy_set(dev, B43_LPPHY_A_PHY_CTL_ADDR, 0x1);
+}
+
+//SPEC FIXME what does a negative freq mean?
+static void lpphy_start_tx_tone(struct b43_wldev *dev, s32 freq, u16 max)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ u16 buf[64];
+ int i, samples = 0, angle = 0, rotation = (9 * freq) / 500;
+ lpphy_c32 sample;
+
+ lpphy->tx_tone_freq = freq;
+
+ if (freq) {
+ /* Find i for which abs(freq) integrally divides 20000 * i */
+ for (i = 1; samples * abs(freq) != 20000 * i; i++) {
+ samples = (20000 * i) / abs(freq);
+ if(B43_WARN_ON(samples > 63))
+ return;
+ }
+ } else {
+ samples = 2;
+ }
+
+ for (i = 0; i < samples; i++) {
+ sample = lpphy_cordic(angle);
+ angle += rotation;
+ buf[i] = ((sample.i * max) & 0xFF) << 8;
+ buf[i] |= (sample.q * max) & 0xFF;
+ }
+
+ b43_lptab_write_bulk(dev, B43_LPTAB16(5, 0), samples, buf);
+
+ lpphy_run_samples(dev, samples, 0xFFFF, 0);
+}
+
+static void lpphy_stop_tx_tone(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ int i;
+
+ lpphy->tx_tone_freq = 0;
+
+ b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000);
+ for (i = 0; i < 31; i++) {
+ if (!(b43_phy_read(dev, B43_LPPHY_A_PHY_CTL_ADDR) & 0x1))
+ break;
+ udelay(100);
+ }
+}
+
+
+static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains,
+ int mode, bool useindex, u8 index)
+{
+ //TODO
+}
+
+static void lpphy_papd_cal_txpwr(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ struct ssb_bus *bus = dev->dev->bus;
+ struct lpphy_tx_gains gains, oldgains;
+ int old_txpctl, old_afe_ovr, old_rf, old_bbmult;
+
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
+ old_txpctl = lpphy->txpctl_mode;
+ old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
+ if (old_afe_ovr)
+ oldgains = lpphy_get_tx_gains(dev);
+ old_rf = b43_phy_read(dev, B43_LPPHY_RF_PWR_OVERRIDE) & 0xFF;
+ old_bbmult = lpphy_get_bb_mult(dev);
+
+ lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+
+ if (bus->chip_id == 0x4325 && bus->chip_rev == 0)
+ lpphy_papd_cal(dev, gains, 0, 1, 30);
+ else
+ lpphy_papd_cal(dev, gains, 0, 1, 65);
+
+ if (old_afe_ovr)
+ lpphy_set_tx_gains(dev, oldgains);
+ lpphy_set_bb_mult(dev, old_bbmult);
+ lpphy_set_tx_power_control(dev, old_txpctl);
+ b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, old_rf);
+}
+
+static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx,
+ bool rx, bool pa, struct lpphy_tx_gains *gains)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ struct ssb_bus *bus = dev->dev->bus;
+ const struct lpphy_rx_iq_comp *iqcomp = NULL;
+ struct lpphy_tx_gains nogains, oldgains;
+ u16 tmp;
+ int i, ret;
+
+ memset(&nogains, 0, sizeof(nogains));
+ memset(&oldgains, 0, sizeof(oldgains));
+
+ if (bus->chip_id == 0x5354) {
+ for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) {
+ if (lpphy_5354_iq_table[i].chan == lpphy->channel) {
+ iqcomp = &lpphy_5354_iq_table[i];
+ }
+ }
+ } else if (dev->phy.rev >= 2) {
+ iqcomp = &lpphy_rev2plus_iq_comp;
+ } else {
+ for (i = 0; i < ARRAY_SIZE(lpphy_rev0_1_iq_table); i++) {
+ if (lpphy_rev0_1_iq_table[i].chan == lpphy->channel) {
+ iqcomp = &lpphy_rev0_1_iq_table[i];
+ }
+ }
+ }
+
+ if (B43_WARN_ON(!iqcomp))
+ return 0;
+
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, iqcomp->c1);
+ b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S,
+ 0x00FF, iqcomp->c0 << 8);
+
+ if (noise) {
+ tx = true;
+ rx = false;
+ pa = false;
+ }
+
+ lpphy_set_trsw_over(dev, tx, rx);
+
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
+ b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
+ 0xFFF7, pa << 3);
+ } else {
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
+ b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
+ 0xFFDF, pa << 5);
+ }
+
+ tmp = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
+
+ if (noise)
+ lpphy_set_rx_gain(dev, 0x2D5D);
+ else {
+ if (tmp)
+ oldgains = lpphy_get_tx_gains(dev);
+ if (!gains)
+ gains = &nogains;
+ lpphy_set_tx_gains(dev, *gains);
+ }
+
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
+ b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
+ lpphy_set_deaf(dev, false);
+ if (noise)
+ ret = lpphy_calc_rx_iq_comp(dev, 0xFFF0);
+ else {
+ lpphy_start_tx_tone(dev, 4000, 100);
+ ret = lpphy_calc_rx_iq_comp(dev, 0x4000);
+ lpphy_stop_tx_tone(dev);
+ }
+ lpphy_clear_deaf(dev, false);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
+ b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF);
+ if (!noise) {
+ if (tmp)
+ lpphy_set_tx_gains(dev, oldgains);
+ else
+ lpphy_disable_tx_gain_override(dev);
+ }
+ lpphy_disable_rx_gain_override(dev);
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
+ b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF);
+ return ret;
+}
+
+static void lpphy_calibration(struct b43_wldev *dev)
+{
+ struct b43_phy_lp *lpphy = dev->phy.lp;
+ enum b43_lpphy_txpctl_mode saved_pctl_mode;
+ bool full_cal = false;
+
+ if (lpphy->full_calib_chan != lpphy->channel) {
+ full_cal = true;
+ lpphy->full_calib_chan = lpphy->channel;
+ }
+
+ b43_mac_suspend(dev);
+
+ lpphy_btcoex_override(dev);
+ if (dev->phy.rev >= 2)
+ lpphy_save_dig_flt_state(dev);
+ lpphy_read_tx_pctl_mode_from_hardware(dev);
+ saved_pctl_mode = lpphy->txpctl_mode;
+ lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+ //TODO Perform transmit power table I/Q LO calibration
+ if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
+ lpphy_pr41573_workaround(dev);
+ if ((dev->phy.rev >= 2) && full_cal) {
+ lpphy_papd_cal_txpwr(dev);
+ }
+ lpphy_set_tx_power_control(dev, saved_pctl_mode);
+ if (dev->phy.rev >= 2)
+ lpphy_restore_dig_flt_state(dev);
+ lpphy_rx_iq_cal(dev, true, true, false, false, NULL);
+
+ b43_mac_enable(dev);
+}
+
static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
@@ -1539,12 +2081,6 @@ static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}
-static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
- bool blocked)
-{
- //TODO
-}
-
struct b206x_channel {
u8 channel;
u16 freq;
@@ -2010,22 +2546,6 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
return err;
}
-
-/* This was previously called lpphy_japan_filter */
-static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
-{
- struct b43_phy_lp *lpphy = dev->phy.lp;
- u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
-
- if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
- b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
- if ((dev->phy.rev == 1) && (lpphy->rc_cap))
- lpphy_set_rc_cap(dev);
- } else {
- b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
- }
-}
-
static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
{
u16 tmp;
@@ -2210,18 +2730,6 @@ static int b43_lpphy_op_init(struct b43_wldev *dev)
return 0;
}
-static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
-{
- if (dev->phy.rev >= 2)
- return; // rev2+ doesn't support antenna diversity
-
- if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
- return;
-
- b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
- b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
-}
-
static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
{
//TODO
@@ -2244,6 +2752,11 @@ void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on)
}
}
+static void b43_lpphy_op_pwork_15sec(struct b43_wldev *dev)
+{
+ //TODO
+}
+
const struct b43_phy_operations b43_phyops_lp = {
.allocate = b43_lpphy_op_allocate,
.free = b43_lpphy_op_free,
@@ -2261,4 +2774,6 @@ const struct b43_phy_operations b43_phyops_lp = {
.set_rx_antenna = b43_lpphy_op_set_rx_antenna,
.recalc_txpower = b43_lpphy_op_recalc_txpower,
.adjust_txpower = b43_lpphy_op_adjust_txpower,
+ .pwork_15sec = b43_lpphy_op_pwork_15sec,
+ .pwork_60sec = lpphy_calibration,
};
diff --git a/drivers/net/wireless/b43/phy_lp.h b/drivers/net/wireless/b43/phy_lp.h
index c3232c1..62737f7 100644
--- a/drivers/net/wireless/b43/phy_lp.h
+++ b/drivers/net/wireless/b43/phy_lp.h
@@ -286,6 +286,7 @@
#define B43_LPPHY_TR_LOOKUP_6 B43_PHY_OFDM(0xC8) /* TR Lookup 6 */
#define B43_LPPHY_TR_LOOKUP_7 B43_PHY_OFDM(0xC9) /* TR Lookup 7 */
#define B43_LPPHY_TR_LOOKUP_8 B43_PHY_OFDM(0xCA) /* TR Lookup 8 */
+#define B43_LPPHY_RF_PWR_OVERRIDE B43_PHY_OFDM(0xD3) /* RF power override */
@@ -871,12 +872,12 @@ struct b43_phy_lp {
u8 rssi_gs;
/* RC cap */
- u8 rc_cap; /* FIXME initial value? */
+ u8 rc_cap;
/* BX arch */
u8 bx_arch;
/* Full calibration channel */
- u8 full_calib_chan; /* FIXME initial value? */
+ u8 full_calib_chan;
/* Transmit iqlocal best coeffs */
bool tx_iqloc_best_coeffs_valid;
@@ -891,6 +892,12 @@ struct b43_phy_lp {
/* The channel we are tuned to */
u8 channel;
+
+ /* The active antenna diversity mode */
+ int antenna;
+
+ /* Frequency of the active TX tone */
+ int tx_tone_freq;
};
enum tssi_mux_mode {
--
1.6.4.2
^ permalink raw reply related
* rt61pci bug
From: Tim Blechmann @ 2009-10-25 11:02 UTC (permalink / raw)
To: linux-wireless
[-- Attachment #1.1: Type: text/plain, Size: 4737 bytes --]
running the rt61pci module on 2.6.31.5 works fine, but using the recent
linus/master (2.6.32-rc5) results in this:
[ 2112.943630] phy0 -> rt2x00queue_write_tx_frame: Error - Arrived at non-free entry in the non-full queue 2.
[...]
[ 2827.646318] phy0 -> rt61pci_wait_bbp_ready: Error - BBP register access failed, aborting.
[ 2827.646323] phy0 -> rt61pci_set_device_state: Error - Device failed to enter state 4 (-5).
[ 2873.143407] BUG: unable to handle kernel NULL pointer dereference at 0000000000000020
[ 2873.143413] IP: [<ffffffffa01e7290>] rt2x00pci_free_queue_dma+0x20/0xd0 [rt2x00pci]
[ 2873.143421] PGD 2dec1a067 PUD 26c1bc067 PMD 0
[ 2873.143426] Oops: 0000 [#1] PREEMPT SMP
[ 2873.143429] last sysfs file: /sys/devices/platform/coretemp.3/temp1_input
[ 2873.143433] CPU 0
[ 2873.143434] Modules linked in: binfmt_misc ppdev nvidia(P) ipt_REJECT ipt_LOG xt_limit xt_tcpudp xt_state ipt_addrtype snd_hda_codec_realtek ip6table_filter ip6_tables nf_nat_irc coretemp arc4 snd_hda_intel nf_conntrack_irc snd_hda_codec snd_hdsp nf_nat_ftp nf_nat nf_conntrack_ipv4 nf_defrag_ipv4 snd_pcm_oss rt61pci(-) crc_itu_t snd_mixer_oss nf_conntrack_ftp lp snd_pcm nf_conntrack rt2x00pci snd_hwdep parport iptable_filter rt2x00lib snd_seq_dummy snd_seq_oss snd_seq_midi ip_tables x_tables led_class snd_rawmidi snd_seq_midi_event snd_seq mac80211 snd_timer snd_seq_device cfg80211 eeprom_93cx6 snd psmouse pcmcia soundcore snd_page_alloc serio_raw yenta_socket rsrc_nonstatic pcmcia_core xfs exportfs usbhid r8169 mii floppy
[ 2873.143487] Pid: 4677, comm: rmmod Tainted: P 2.6.32-rc5 #35 System Product Name
[ 2873.143490] RIP: 0010:[<ffffffffa01e7290>] [<ffffffffa01e7290>] rt2x00pci_free_queue_dma+0x20/0xd0 [rt2x00pci]
[ 2873.143496] RSP: 0018:ffff880305e53cf8 EFLAGS: 00010282
[ 2873.143499] RAX: 0000000000000000 RBX: ffff8803312e51e0 RCX: 0000000000000000
[ 2873.143501] RDX: 0000000000000150 RSI: ffff880331290c00 RDI: ffff8803312e51e0
[ 2873.143504] RBP: ffff880305e53d38 R08: 0000000000000000 R09: 0000000000000000
[ 2873.143506] R10: 0000000000000001 R11: 0000000000000000 R12: ffff880331290c38
[ 2873.143508] R13: ffff8803312e4340 R14: ffff8803312e51e0 R15: 0000000000000001
[ 2873.143511] FS: 00007f4e38e146f0(0000) GS:ffff880028200000(0000) knlGS:0000000000000000
[ 2873.143514] CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b
[ 2873.143517] CR2: 0000000000000020 CR3: 00000002b2e66000 CR4: 00000000000006b0
[ 2873.143519] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 2873.143522] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
[ 2873.143525] Process rmmod (pid: 4677, threadinfo ffff880305e52000, task ffff880305f50000)
[ 2873.143527] Stack:
[ 2873.143528] ffff8803312e51e0 0000000000000001 ffff880305e53d38 ffff8803312e51e0
[ 2873.143532] <0> ffff880331290c38 ffff8803312e4340 ffff8803312e51e0 0000000000000001
[ 2873.143537] <0> ffff880305e53d58 ffffffffa01e7378 ffff8803312e51e0 ffff880333afc080
[ 2873.143542] Call Trace:
[ 2873.143548] [<ffffffffa01e7378>] rt2x00pci_uninitialize+0x38/0x70 [rt2x00pci]
[ 2873.143554] [<ffffffffa01c8062>] rt2x00lib_uninitialize+0x32/0x60 [rt2x00lib]
[ 2873.143560] [<ffffffffa01c886d>] rt2x00lib_remove_dev+0x2d/0xc0 [rt2x00lib]
[ 2873.143565] [<ffffffffa01e718c>] rt2x00pci_remove+0x3c/0x120 [rt2x00pci]
[ 2873.143572] [<ffffffff81298fbf>] pci_device_remove+0x2f/0x60
[ 2873.143578] [<ffffffff8132eec3>] __device_release_driver+0x53/0xb0
[ 2873.143582] [<ffffffff8132efe0>] driver_detach+0xc0/0xd0
[ 2873.143587] [<ffffffff8132df44>] bus_remove_driver+0x94/0xc0
[ 2873.143591] [<ffffffff8132f5a9>] driver_unregister+0x59/0x90
[ 2873.143595] [<ffffffff8129925f>] pci_unregister_driver+0x3f/0xb0
[ 2873.143601] [<ffffffffa024f290>] rt61pci_exit+0x10/0x12 [rt61pci]
[ 2873.143608] [<ffffffff810923f3>] sys_delete_module+0x183/0x250
[ 2873.143613] [<ffffffff8107dbe9>] ? up_read+0x9/0x10
[ 2873.143618] [<ffffffff815351df>] ? do_page_fault+0x13f/0x3f0
[ 2873.143624] [<ffffffff81011f02>] system_call_fastpath+0x16/0x1b
[ 2873.143627] Code: b8 ea ff ff ff eb b3 0f 1f 40 00 55 48 89 e5 48 83 ec 40 48 89 5d d8 4c 89 65 e0 4c 89 6d e8 4c 89 75 f0 4c 89 7d f8 48 8b 46 08 <48> 8b 58 20 48 8b 13 48 85 d2 74 4c 4c 8b 27 48 8b 4b 08 44 0f
[ 2873.143663] RIP [<ffffffffa01e7290>] rt2x00pci_free_queue_dma+0x20/0xd0 [rt2x00pci]
[ 2873.143669] RSP <ffff880305e53cf8>
[ 2873.143670] CR2: 0000000000000020
[ 2873.143673] ---[ end trace af6b473a456cf4f3 ]---
full bootlog attached.
hth, tim
--
tim@klingt.org
http://tim.klingt.org
After one look at this planet any visitor from outer space would say
"I want to see the manager."
William S. Burroughs
[-- Attachment #1.2: rt61 --]
[-- Type: text/plain, Size: 70475 bytes --]
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Linux version 2.6.32-rc5 (tim@moka) (gcc version 4.4.1 (Ubuntu 4.4.1-4ubuntu8) ) #35 SMP PREEMPT Sat Oct 24 22:49:23 CEST 2009
[ 0.000000] Command line: root=UUID=f4e801b1-b54a-4002-a3e3-328308ad48fb ro splash vga=769
[ 0.000000] KERNEL supported cpus:
[ 0.000000] Intel GenuineIntel
[ 0.000000] AMD AuthenticAMD
[ 0.000000] Centaur CentaurHauls
[ 0.000000] BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
[ 0.000000] BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
[ 0.000000] BIOS-e820: 00000000000e4c00 - 0000000000100000 (reserved)
[ 0.000000] BIOS-e820: 0000000000100000 - 00000000bf680000 (usable)
[ 0.000000] BIOS-e820: 00000000bf680000 - 00000000bf698000 (ACPI data)
[ 0.000000] BIOS-e820: 00000000bf698000 - 00000000bf6dc000 (ACPI NVS)
[ 0.000000] BIOS-e820: 00000000bf6dc000 - 00000000c0000000 (reserved)
[ 0.000000] BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
[ 0.000000] BIOS-e820: 00000000ffe00000 - 0000000100000000 (reserved)
[ 0.000000] BIOS-e820: 0000000100000000 - 0000000340000000 (usable)
[ 0.000000] DMI 2.5 present.
[ 0.000000] AMI BIOS detected: BIOS may corrupt low RAM, working around it.
[ 0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
[ 0.000000] last_pfn = 0x340000 max_arch_pfn = 0x400000000
[ 0.000000] MTRR default type: uncachable
[ 0.000000] MTRR fixed ranges enabled:
[ 0.000000] 00000-9FFFF write-back
[ 0.000000] A0000-BFFFF uncachable
[ 0.000000] C0000-E3FFF write-protect
[ 0.000000] E4000-EBFFF write-through
[ 0.000000] EC000-FFFFF write-protect
[ 0.000000] MTRR variable ranges enabled:
[ 0.000000] 0 base 000000000 mask E00000000 write-back
[ 0.000000] 1 base 200000000 mask F00000000 write-back
[ 0.000000] 2 base 300000000 mask FC0000000 write-back
[ 0.000000] 3 base 0C0000000 mask FC0000000 uncachable
[ 0.000000] 4 base 0BF700000 mask FFFF00000 uncachable
[ 0.000000] 5 base 0BF800000 mask FFF800000 uncachable
[ 0.000000] 6 disabled
[ 0.000000] 7 disabled
[ 0.000000] e820 update range: 00000000bf700000 - 0000000100000000 (usable) ==> (reserved)
[ 0.000000] last_pfn = 0xbf680 max_arch_pfn = 0x400000000
[ 0.000000] Scanning 0 areas for low memory corruption
[ 0.000000] modified physical RAM map:
[ 0.000000] modified: 0000000000000000 - 0000000000010000 (reserved)
[ 0.000000] modified: 0000000000010000 - 000000000009fc00 (usable)
[ 0.000000] modified: 000000000009fc00 - 00000000000a0000 (reserved)
[ 0.000000] modified: 00000000000e4c00 - 0000000000100000 (reserved)
[ 0.000000] modified: 0000000000100000 - 00000000bf680000 (usable)
[ 0.000000] modified: 00000000bf680000 - 00000000bf698000 (ACPI data)
[ 0.000000] modified: 00000000bf698000 - 00000000bf6dc000 (ACPI NVS)
[ 0.000000] modified: 00000000bf6dc000 - 00000000c0000000 (reserved)
[ 0.000000] modified: 00000000fee00000 - 00000000fee01000 (reserved)
[ 0.000000] modified: 00000000ffe00000 - 0000000100000000 (reserved)
[ 0.000000] modified: 0000000100000000 - 0000000340000000 (usable)
[ 0.000000] initial memory mapped : 0 - 20000000
[ 0.000000] init_memory_mapping: 0000000000000000-00000000bf680000
[ 0.000000] 0000000000 - 00bf600000 page 2M
[ 0.000000] 00bf600000 - 00bf680000 page 4k
[ 0.000000] kernel direct mapping tables up to bf680000 @ 10000-15000
[ 0.000000] init_memory_mapping: 0000000100000000-0000000340000000
[ 0.000000] 0100000000 - 0340000000 page 2M
[ 0.000000] kernel direct mapping tables up to 340000000 @ 13000-21000
[ 0.000000] RAMDISK: 37868000 - 37fef1a2
[ 0.000000] ACPI: RSDP 00000000000fabd0 00024 (v02 ACPIAM)
[ 0.000000] ACPI: XSDT 00000000bf680100 0005C (v01 022609 XSDT1156 20090226 MSFT 00000097)
[ 0.000000] ACPI: FACP 00000000bf680290 000F4 (v03 022609 FACP1156 20090226 MSFT 00000097)
[ 0.000000] ACPI: DSDT 00000000bf6804b0 0C3DD (v01 A1146 A1146001 00000001 INTL 20060113)
[ 0.000000] ACPI: FACS 00000000bf698000 00040
[ 0.000000] ACPI: APIC 00000000bf680390 000D8 (v01 022609 APIC1156 20090226 MSFT 00000097)
[ 0.000000] ACPI: MCFG 00000000bf680470 0003C (v01 022609 OEMMCFG 20090226 MSFT 00000097)
[ 0.000000] ACPI: OEMB 00000000bf698040 00072 (v01 022609 OEMB1156 20090226 MSFT 00000097)
[ 0.000000] ACPI: HPET 00000000bf68f4b0 00038 (v01 022609 OEMHPET 20090226 MSFT 00000097)
[ 0.000000] ACPI: OSFR 00000000bf68f4f0 000B0 (v01 022609 OEMOSFR 20090226 MSFT 00000097)
[ 0.000000] ACPI: SSDT 00000000bf69a8f0 0249F (v01 DpgPmm CpuPm 00000012 INTL 20060113)
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] (8 early reservations) ==> bootmem [0000000000 - 0340000000]
[ 0.000000] #0 [0000000000 - 0000001000] BIOS data page ==> [0000000000 - 0000001000]
[ 0.000000] #1 [0000006000 - 0000008000] TRAMPOLINE ==> [0000006000 - 0000008000]
[ 0.000000] #2 [0001000000 - 00019a3d44] TEXT DATA BSS ==> [0001000000 - 00019a3d44]
[ 0.000000] #3 [0037868000 - 0037fef1a2] RAMDISK ==> [0037868000 - 0037fef1a2]
[ 0.000000] #4 [000009fc00 - 0000100000] BIOS reserved ==> [000009fc00 - 0000100000]
[ 0.000000] #5 [00019a4000 - 00019a4288] BRK ==> [00019a4000 - 00019a4288]
[ 0.000000] #6 [0000010000 - 0000013000] PGTABLE ==> [0000010000 - 0000013000]
[ 0.000000] #7 [0000013000 - 000001c000] PGTABLE ==> [0000013000 - 000001c000]
[ 0.000000] found SMP MP-table at [ffff8800000ff780] ff780
[ 0.000000] [ffffea0000000000-ffffea000b5fffff] PMD -> [ffff880028600000-ffff880032dfffff] on node 0
[ 0.000000] Zone PFN ranges:
[ 0.000000] DMA 0x00000010 -> 0x00001000
[ 0.000000] DMA32 0x00001000 -> 0x00100000
[ 0.000000] Normal 0x00100000 -> 0x00340000
[ 0.000000] Movable zone start PFN for each node
[ 0.000000] early_node_map[3] active PFN ranges
[ 0.000000] 0: 0x00000010 -> 0x0000009f
[ 0.000000] 0: 0x00000100 -> 0x000bf680
[ 0.000000] 0: 0x00100000 -> 0x00340000
[ 0.000000] On node 0 totalpages: 3143183
[ 0.000000] DMA zone: 56 pages used for memmap
[ 0.000000] DMA zone: 111 pages reserved
[ 0.000000] DMA zone: 3816 pages, LIFO batch:0
[ 0.000000] DMA32 zone: 14280 pages used for memmap
[ 0.000000] DMA32 zone: 765624 pages, LIFO batch:31
[ 0.000000] Normal zone: 32256 pages used for memmap
[ 0.000000] Normal zone: 2327040 pages, LIFO batch:31
[ 0.000000] ACPI: PM-Timer IO Port: 0x808
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x04] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x06] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x01] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x03] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x05] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0x07] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x09] lapic_id[0x88] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x89] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x8a] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x8b] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x8c] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x8d] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x8e] disabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x10] lapic_id[0x8f] disabled)
[ 0.000000] ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
[ 0.000000] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23
[ 0.000000] ACPI: IOAPIC (id[0x09] address[0xfec8a000] gsi_base[24])
[ 0.000000] IOAPIC[1]: apic_id 9, version 32, address 0xfec8a000, GSI 24-47
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 0.000000] ACPI: IRQ0 used by override.
[ 0.000000] ACPI: IRQ2 used by override.
[ 0.000000] ACPI: IRQ9 used by override.
[ 0.000000] Using ACPI (MADT) for SMP configuration information
[ 0.000000] ACPI: HPET id: 0x8086a301 base: 0xfed00000
[ 0.000000] 16 Processors exceeds NR_CPUS limit of 8
[ 0.000000] SMP: Allowing 8 CPUs, 0 hotplug CPUs
[ 0.000000] nr_irqs_gsi: 48
[ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000e5000
[ 0.000000] PM: Registered nosave memory: 00000000000e5000 - 0000000000100000
[ 0.000000] PM: Registered nosave memory: 00000000bf680000 - 00000000bf698000
[ 0.000000] PM: Registered nosave memory: 00000000bf698000 - 00000000bf6dc000
[ 0.000000] PM: Registered nosave memory: 00000000bf6dc000 - 00000000c0000000
[ 0.000000] PM: Registered nosave memory: 00000000c0000000 - 00000000fee00000
[ 0.000000] PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000
[ 0.000000] PM: Registered nosave memory: 00000000fee01000 - 00000000ffe00000
[ 0.000000] PM: Registered nosave memory: 00000000ffe00000 - 0000000100000000
[ 0.000000] Allocating PCI resources starting at c0000000 (gap: c0000000:3ee00000)
[ 0.000000] Booting paravirtualized kernel on bare hardware
[ 0.000000] NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1
[ 0.000000] PERCPU: Embedded 30 pages/cpu @ffff880028200000 s90264 r8192 d24424 u262144
[ 0.000000] pcpu-alloc: s90264 r8192 d24424 u262144 alloc=1*2097152
[ 0.000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 3096480
[ 0.000000] Kernel command line: root=UUID=f4e801b1-b54a-4002-a3e3-328308ad48fb ro splash vga=769
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
[ 0.000000] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
[ 0.000000] Initializing CPU#0
[ 0.000000] Checking aperture...
[ 0.000000] No AGP bridge found
[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area
[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
[ 0.000000] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[ 0.000000] Placing 64MB software IO TLB between ffff880020000000 - ffff880024000000
[ 0.000000] software IO TLB at phys 0x20000000 - 0x24000000
[ 0.000000] Memory: 12290392k/13631488k available (5350k kernel code, 1058756k absent, 281440k reserved, 2978k data, 536k init)
[ 0.000000] SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] NR_IRQS:512
[ 0.000000] Extended CMOS year: 2000
[ 0.000000] Console: colour VGA+ 80x25
[ 0.000000] console [tty0] enabled
[ 0.000000] allocated 125829120 bytes of page_cgroup
[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
[ 0.000000] hpet clockevent registered
[ 0.000000] HPET: 4 timers in total, 0 timers will be used for per-cpu timer
[ 0.000000] Fast TSC calibration using PIT
[ 0.010000] Detected 2672.696 MHz processor.
[ 0.000002] Calibrating delay loop (skipped), value calculated using timer frequency.. 5345.39 BogoMIPS (lpj=26726960)
[ 0.000121] Security Framework initialized
[ 0.000174] SELinux: Disabled at boot.
[ 0.000228] Mount-cache hash table entries: 256
[ 0.000356] Initializing cgroup subsys ns
[ 0.000409] Initializing cgroup subsys cpuacct
[ 0.000462] Initializing cgroup subsys memory
[ 0.000516] Initializing cgroup subsys freezer
[ 0.000579] CPU: Physical Processor ID: 0
[ 0.000630] CPU: Processor Core ID: 0
[ 0.000683] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 0.000766] CPU: L2 cache: 256K
[ 0.000816] CPU: L3 cache: 8192K
[ 0.000866] using mwait in idle threads.
[ 0.000917] Performance Events: Nehalem/Corei7 events, Intel PMU driver.
[ 0.001036] ... version: 3
[ 0.001087] ... bit width: 48
[ 0.001138] ... generic registers: 4
[ 0.001189] ... value mask: 0000ffffffffffff
[ 0.001242] ... max period: 000000007fffffff
[ 0.001295] ... fixed-purpose events: 3
[ 0.001346] ... event mask: 000000070000000f
[ 0.002091] ACPI: Core revision 20090903
[ 0.038173] Setting APIC routing to flat
[ 0.038669] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[ 0.140160] CPU0: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 0.308782] Booting processor 1 APIC 0x2 ip 0x6000
[ 0.322349] Initializing CPU#1
[ 0.468710] Calibrating delay using timer specific routine.. 5345.39 BogoMIPS (lpj=26726951)
[ 0.468716] CPU: Physical Processor ID: 0
[ 0.468717] CPU: Processor Core ID: 1
[ 0.468719] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 0.468720] CPU: L2 cache: 256K
[ 0.468721] CPU: L3 cache: 8192K
[ 0.468801] CPU1: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 0.470036] Skipping synchronization checks as TSC is reliable.
[ 0.498718] Booting processor 2 APIC 0x4 ip 0x6000
[ 0.509131] Initializing CPU#2
[ 0.658647] Calibrating delay using timer specific routine.. 5345.37 BogoMIPS (lpj=26726889)
[ 0.658655] CPU: Physical Processor ID: 0
[ 0.658656] CPU: Processor Core ID: 2
[ 0.658658] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 0.658660] CPU: L2 cache: 256K
[ 0.658660] CPU: L3 cache: 8192K
[ 0.658738] CPU2: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 0.688656] Booting processor 3 APIC 0x6 ip 0x6000
[ 0.699068] Initializing CPU#3
[ 0.848583] Calibrating delay using timer specific routine.. 5345.37 BogoMIPS (lpj=26726857)
[ 0.848591] CPU: Physical Processor ID: 0
[ 0.848592] CPU: Processor Core ID: 3
[ 0.848594] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 0.848596] CPU: L2 cache: 256K
[ 0.848597] CPU: L3 cache: 8192K
[ 0.848636] CPU3: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 0.878593] Booting processor 4 APIC 0x1 ip 0x6000
[ 0.889006] Initializing CPU#4
[ 1.038518] Calibrating delay using timer specific routine.. 5345.37 BogoMIPS (lpj=26726859)
[ 1.038525] CPU: Physical Processor ID: 0
[ 1.038527] CPU: Processor Core ID: 0
[ 1.038529] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 1.038531] CPU: L2 cache: 256K
[ 1.038532] CPU: L3 cache: 8192K
[ 1.038632] CPU4: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 1.068527] Booting processor 5 APIC 0x3 ip 0x6000
[ 1.078941] Initializing CPU#5
[ 1.228455] Calibrating delay using timer specific routine.. 5345.37 BogoMIPS (lpj=26726878)
[ 1.228462] CPU: Physical Processor ID: 0
[ 1.228463] CPU: Processor Core ID: 1
[ 1.228465] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 1.228467] CPU: L2 cache: 256K
[ 1.228468] CPU: L3 cache: 8192K
[ 1.228485] CPU5: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 1.258464] Booting processor 6 APIC 0x5 ip 0x6000
[ 1.268779] Initializing CPU#6
[ 1.418391] Calibrating delay using timer specific routine.. 5345.26 BogoMIPS (lpj=26726328)
[ 1.418399] CPU: Physical Processor ID: 0
[ 1.418400] CPU: Processor Core ID: 2
[ 1.418402] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 1.418403] CPU: L2 cache: 256K
[ 1.418404] CPU: L3 cache: 8192K
[ 1.418478] CPU6: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 1.448399] Booting processor 7 APIC 0x7 ip 0x6000
[ 1.458814] Initializing CPU#7
[ 1.608327] Calibrating delay using timer specific routine.. 5345.26 BogoMIPS (lpj=26726307)
[ 1.608335] CPU: Physical Processor ID: 0
[ 1.608336] CPU: Processor Core ID: 3
[ 1.608338] CPU: L1 I cache: 32K, L1 D cache: 32K
[ 1.608339] CPU: L2 cache: 256K
[ 1.608340] CPU: L3 cache: 8192K
[ 1.608365] CPU7: Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz stepping 05
[ 1.608870] Brought up 8 CPUs
[ 1.608919] Total of 8 processors activated (42762.80 BogoMIPS).
[ 1.612204] CPU0 attaching sched-domain:
[ 1.612207] domain 0: span 0,4 level SIBLING
[ 1.612209] groups: 0 (cpu_power = 589) 4 (cpu_power = 589)
[ 1.612213] domain 1: span 0-7 level MC
[ 1.612214] groups: 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178)
[ 1.612222] CPU1 attaching sched-domain:
[ 1.612223] domain 0: span 1,5 level SIBLING
[ 1.612224] groups: 1 (cpu_power = 589) 5 (cpu_power = 589)
[ 1.612228] domain 1: span 0-7 level MC
[ 1.612229] groups: 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178)
[ 1.612235] CPU2 attaching sched-domain:
[ 1.612236] domain 0: span 2,6 level SIBLING
[ 1.612238] groups: 2 (cpu_power = 589) 6 (cpu_power = 589)
[ 1.612241] domain 1: span 0-7 level MC
[ 1.612243] groups: 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178)
[ 1.612248] CPU3 attaching sched-domain:
[ 1.612250] domain 0: span 3,7 level SIBLING
[ 1.612251] groups: 3 (cpu_power = 589) 7 (cpu_power = 589)
[ 1.612254] domain 1: span 0-7 level MC
[ 1.612256] groups: 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178)
[ 1.612262] CPU4 attaching sched-domain:
[ 1.612263] domain 0: span 0,4 level SIBLING
[ 1.612264] groups: 4 (cpu_power = 589) 0 (cpu_power = 589)
[ 1.612268] domain 1: span 0-7 level MC
[ 1.612269] groups: 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178)
[ 1.612275] CPU5 attaching sched-domain:
[ 1.612276] domain 0: span 1,5 level SIBLING
[ 1.612278] groups: 5 (cpu_power = 589) 1 (cpu_power = 589)
[ 1.612281] domain 1: span 0-7 level MC
[ 1.612282] groups: 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178)
[ 1.612288] CPU6 attaching sched-domain:
[ 1.612289] domain 0: span 2,6 level SIBLING
[ 1.612291] groups: 6 (cpu_power = 589) 2 (cpu_power = 589)
[ 1.612294] domain 1: span 0-7 level MC
[ 1.612295] groups: 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178)
[ 1.612301] CPU7 attaching sched-domain:
[ 1.612303] domain 0: span 3,7 level SIBLING
[ 1.612304] groups: 7 (cpu_power = 589) 3 (cpu_power = 589)
[ 1.612307] domain 1: span 0-7 level MC
[ 1.612309] groups: 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178)
[ 1.612781] regulator: core version 0.5
[ 1.612854] Time: 9:30:28 Date: 10/25/09
[ 1.612933] NET: Registered protocol family 16
[ 1.613057] ACPI: bus type pci registered
[ 1.613154] PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255
[ 1.613211] PCI: Not using MMCONFIG.
[ 1.613261] PCI: Using configuration type 1 for base access
[ 1.613893] bio: create slab <bio-0> at 0
[ 1.614811] ACPI: EC: Look up EC in DSDT
[ 1.617184] ACPI: Executed 1 blocks of module-level executable AML code
[ 1.647165] ACPI: Interpreter enabled
[ 1.647220] ACPI: (supports S0 S1 S3 S4 S5)
[ 1.647443] ACPI: Using IOAPIC for interrupt routing
[ 1.647544] PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255
[ 1.649763] PCI: MCFG area at e0000000 reserved in ACPI motherboard resources
[ 1.653743] PCI: Using MMCONFIG at e0000000 - efffffff
[ 1.661959] ACPI Warning: Incorrect checksum in table [OEMB] - 8B, should be 83 (20090903/tbutils-314)
[ 1.662223] ACPI: No dock devices found.
[ 1.662401] ACPI: PCI Root Bridge [PCI0] (0000:00)
[ 1.662517] pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
[ 1.662574] pci 0000:00:00.0: PME# disabled
[ 1.662680] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
[ 1.662736] pci 0000:00:01.0: PME# disabled
[ 1.662842] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[ 1.662898] pci 0000:00:03.0: PME# disabled
[ 1.663006] pci 0000:00:07.0: PME# supported from D0 D3hot D3cold
[ 1.663062] pci 0000:00:07.0: PME# disabled
[ 1.663398] pci 0000:00:1a.0: reg 20 io port: [0xb800-0xb81f]
[ 1.663459] pci 0000:00:1a.1: reg 20 io port: [0xb880-0xb89f]
[ 1.663521] pci 0000:00:1a.2: reg 20 io port: [0xbc00-0xbc1f]
[ 1.663586] pci 0000:00:1a.7: reg 10 32bit mmio: [0xf7fff000-0xf7fff3ff]
[ 1.663635] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold
[ 1.663692] pci 0000:00:1a.7: PME# disabled
[ 1.663778] pci 0000:00:1b.0: reg 10 64bit mmio: [0xf7ff8000-0xf7ffbfff]
[ 1.663815] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
[ 1.663871] pci 0000:00:1b.0: PME# disabled
[ 1.663975] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 1.664031] pci 0000:00:1c.0: PME# disabled
[ 1.664137] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold
[ 1.664193] pci 0000:00:1c.2: PME# disabled
[ 1.664293] pci 0000:00:1d.0: reg 20 io port: [0xb080-0xb09f]
[ 1.664355] pci 0000:00:1d.1: reg 20 io port: [0xb400-0xb41f]
[ 1.664416] pci 0000:00:1d.2: reg 20 io port: [0xb480-0xb49f]
[ 1.664482] pci 0000:00:1d.7: reg 10 32bit mmio: [0xf7ffe000-0xf7ffe3ff]
[ 1.664531] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
[ 1.664588] pci 0000:00:1d.7: PME# disabled
[ 1.664748] pci 0000:00:1f.0: quirk: region 0800-087f claimed by ICH6 ACPI/GPIO/TCO
[ 1.664820] pci 0000:00:1f.0: quirk: region 0500-053f claimed by ICH6 GPIO
[ 1.664878] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 1 PIO at 0294 (mask 0003)
[ 1.664951] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 3 PIO at 4700 (mask 001f)
[ 1.665066] pci 0000:00:1f.2: reg 10 io port: [0xa000-0xa007]
[ 1.665071] pci 0000:00:1f.2: reg 14 io port: [0x9c00-0x9c03]
[ 1.665076] pci 0000:00:1f.2: reg 18 io port: [0x9880-0x9887]
[ 1.665080] pci 0000:00:1f.2: reg 1c io port: [0x9800-0x9803]
[ 1.665085] pci 0000:00:1f.2: reg 20 io port: [0x9480-0x948f]
[ 1.665089] pci 0000:00:1f.2: reg 24 io port: [0x9400-0x940f]
[ 1.665130] pci 0000:00:1f.3: reg 10 64bit mmio: [0xf7ffd000-0xf7ffd0ff]
[ 1.665141] pci 0000:00:1f.3: reg 20 io port: [0x400-0x41f]
[ 1.665179] pci 0000:00:1f.5: reg 10 io port: [0xb000-0xb007]
[ 1.665184] pci 0000:00:1f.5: reg 14 io port: [0xac00-0xac03]
[ 1.665188] pci 0000:00:1f.5: reg 18 io port: [0xa880-0xa887]
[ 1.665193] pci 0000:00:1f.5: reg 1c io port: [0xa800-0xa803]
[ 1.665197] pci 0000:00:1f.5: reg 20 io port: [0xa480-0xa48f]
[ 1.665202] pci 0000:00:1f.5: reg 24 io port: [0xa400-0xa40f]
[ 1.665278] pci 0000:02:00.0: reg 10 32bit mmio: [0xfa000000-0xfaffffff]
[ 1.665286] pci 0000:02:00.0: reg 14 64bit mmio pref: [0xd0000000-0xdfffffff]
[ 1.665294] pci 0000:02:00.0: reg 1c 64bit mmio: [0xf8000000-0xf9ffffff]
[ 1.665298] pci 0000:02:00.0: reg 24 io port: [0xcc00-0xcc7f]
[ 1.665303] pci 0000:02:00.0: reg 30 32bit mmio pref: [0xfb480000-0xfb4fffff]
[ 1.665348] pci 0000:00:03.0: bridge io port: [0xc000-0xcfff]
[ 1.665351] pci 0000:00:03.0: bridge 32bit mmio: [0xf8000000-0xfb4fffff]
[ 1.665355] pci 0000:00:03.0: bridge 64bit mmio pref: [0xd0000000-0xdfffffff]
[ 1.665420] pci 0000:00:1c.0: bridge 64bit mmio pref: [0xf4f00000-0xf4ffffff]
[ 1.665461] pci 0000:04:00.0: reg 10 io port: [0xd800-0xd8ff]
[ 1.665479] pci 0000:04:00.0: reg 18 64bit mmio: [0xfb5ff000-0xfb5fffff]
[ 1.665492] pci 0000:04:00.0: reg 20 64bit mmio pref: [0xf4ef0000-0xf4efffff]
[ 1.665499] pci 0000:04:00.0: reg 30 32bit mmio pref: [0xfb5c0000-0xfb5dffff]
[ 1.665536] pci 0000:04:00.0: supports D1 D2
[ 1.665537] pci 0000:04:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 1.665595] pci 0000:04:00.0: PME# disabled
[ 1.665694] pci 0000:00:1c.2: bridge io port: [0xd000-0xdfff]
[ 1.665697] pci 0000:00:1c.2: bridge 32bit mmio: [0xfb500000-0xfb5fffff]
[ 1.665702] pci 0000:00:1c.2: bridge 64bit mmio pref: [0xf4e00000-0xf4efffff]
[ 1.665732] pci 0000:06:00.0: reg 10 32bit mmio: [0xfb6f8000-0xfb6fffff]
[ 1.665804] pci 0000:06:01.0: reg 10 32bit mmio: [0x000000-0x000fff]
[ 1.665822] pci 0000:06:01.0: supports D1 D2
[ 1.665823] pci 0000:06:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 1.665881] pci 0000:06:01.0: PME# disabled
[ 1.665973] pci 0000:00:1e.0: transparent bridge
[ 1.666026] pci 0000:00:1e.0: bridge io port: [0xe000-0xefff]
[ 1.666029] pci 0000:00:1e.0: bridge 32bit mmio: [0xfb600000-0xfbefffff]
[ 1.666034] pci 0000:00:1e.0: bridge 64bit mmio pref: [0xf5000000-0xf6ffffff]
[ 1.666069] pci_bus 0000:00: on NUMA node 0
[ 1.666073] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[ 1.666316] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P1._PRT]
[ 1.666411] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P4._PRT]
[ 1.666464] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P6._PRT]
[ 1.666523] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.NPE1._PRT]
[ 1.666571] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.NPE3._PRT]
[ 1.666620] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.NPE7._PRT]
[ 1.691476] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 6 7 10 *11 12 14 15)
[ 1.691976] ACPI: PCI Interrupt Link [LNKB] (IRQs *5)
[ 1.692225] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 6 7 *10 11 12 14 15)
[ 1.692722] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 6 7 10 11 12 *14 15)
[ 1.693219] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 6 7 10 11 12 14 *15)
[ 1.693718] ACPI: PCI Interrupt Link [LNKF] (IRQs *3 4 6 7 10 11 12 14 15)
[ 1.694216] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 6 *7 10 11 12 14 15)
[ 1.694713] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 *4 6 7 10 11 12 14 15)
[ 1.695183] vgaarb: device added: PCI:0000:02:00.0,decodes=io+mem,owns=io+mem,locks=none
[ 1.695256] vgaarb: loaded
[ 1.695365] SCSI subsystem initialized
[ 1.695523] libata version 3.00 loaded.
[ 1.695570] usbcore: registered new interface driver usbfs
[ 1.695633] usbcore: registered new interface driver hub
[ 1.695702] usbcore: registered new device driver usb
[ 1.695846] ACPI: WMI: Mapper loaded
[ 1.695897] PCI: Using ACPI for IRQ routing
[ 1.696078] Bluetooth: Core ver 2.15
[ 1.696147] NET: Registered protocol family 31
[ 1.696199] Bluetooth: HCI device and connection manager initialized
[ 1.696255] Bluetooth: HCI socket layer initialized
[ 1.696308] NET: Registered protocol family 8
[ 1.696360] NET: Registered protocol family 20
[ 1.696417] NetLabel: Initializing
[ 1.696467] NetLabel: domain hash size = 128
[ 1.696518] NetLabel: protocols = UNLABELED CIPSOv4
[ 1.696580] NetLabel: unlabeled traffic allowed by default
[ 1.696657] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
[ 1.696865] hpet0: 4 comparators, 64-bit 14.318180 MHz counter
[ 1.768314] Switching to clocksource tsc
[ 1.769558] pnp: PnP ACPI init
[ 1.769616] ACPI: bus type pnp registered
[ 1.772188] pnp: PnP ACPI: found 15 devices
[ 1.772241] ACPI: ACPI bus type pnp unregistered
[ 1.772299] system 00:01: iomem range 0xfbf00000-0xfbffffff has been reserved
[ 1.772356] system 00:01: iomem range 0xfc000000-0xfcffffff has been reserved
[ 1.772413] system 00:01: iomem range 0xfd000000-0xfdffffff has been reserved
[ 1.772470] system 00:01: iomem range 0xfe000000-0xfebfffff has been reserved
[ 1.772528] system 00:01: iomem range 0xfec8a000-0xfec8afff could not be reserved
[ 1.772598] system 00:01: iomem range 0xfed10000-0xfed10fff has been reserved
[ 1.772658] system 00:07: ioport range 0x290-0x29f has been reserved
[ 1.772716] system 00:08: ioport range 0x4d0-0x4d1 has been reserved
[ 1.772772] system 00:08: ioport range 0x800-0x87f has been reserved
[ 1.772827] system 00:08: ioport range 0x500-0x57f could not be reserved
[ 1.772884] system 00:08: iomem range 0xfed1c000-0xfed1ffff has been reserved
[ 1.772941] system 00:08: iomem range 0xfed20000-0xfed3ffff has been reserved
[ 1.772998] system 00:08: iomem range 0xfed40000-0xfed8ffff has been reserved
[ 1.773057] system 00:0b: iomem range 0xffc00000-0xffdfffff has been reserved
[ 1.773116] system 00:0c: iomem range 0xfec00000-0xfec00fff could not be reserved
[ 1.773187] system 00:0c: iomem range 0xfee00000-0xfee00fff has been reserved
[ 1.773245] system 00:0d: iomem range 0xe0000000-0xefffffff has been reserved
[ 1.773304] system 00:0e: iomem range 0x0-0x9ffff could not be reserved
[ 1.773360] system 00:0e: iomem range 0xc0000-0xcffff has been reserved
[ 1.773416] system 00:0e: iomem range 0xe0000-0xfffff could not be reserved
[ 1.773473] system 00:0e: iomem range 0x100000-0xbfefffff could not be reserved
[ 1.773543] system 00:0e: iomem range 0xfed90000-0xffffffff could not be reserved
[ 1.778265] pci 0000:00:01.0: PCI bridge, secondary bus 0000:01
[ 1.778325] pci 0000:00:01.0: IO window: disabled
[ 1.778380] pci 0000:00:01.0: MEM window: disabled
[ 1.778434] pci 0000:00:01.0: PREFETCH window: disabled
[ 1.778489] pci 0000:00:03.0: PCI bridge, secondary bus 0000:02
[ 1.778545] pci 0000:00:03.0: IO window: 0xc000-0xcfff
[ 1.778600] pci 0000:00:03.0: MEM window: 0xf8000000-0xfb4fffff
[ 1.779402] pci 0000:00:03.0: PREFETCH window: 0x000000d0000000-0x000000dfffffff
[ 1.779475] pci 0000:00:07.0: PCI bridge, secondary bus 0000:03
[ 1.779530] pci 0000:00:07.0: IO window: disabled
[ 1.779585] pci 0000:00:07.0: MEM window: disabled
[ 1.779639] pci 0000:00:07.0: PREFETCH window: disabled
[ 1.779694] pci 0000:00:1c.0: PCI bridge, secondary bus 0000:05
[ 1.779750] pci 0000:00:1c.0: IO window: 0x1000-0x1fff
[ 1.779806] pci 0000:00:1c.0: MEM window: 0xc4000000-0xc41fffff
[ 1.779863] pci 0000:00:1c.0: PREFETCH window: 0x000000c4200000-0x000000c43fffff
[ 1.779938] pci 0000:00:1c.2: PCI bridge, secondary bus 0000:04
[ 1.779994] pci 0000:00:1c.2: IO window: 0xd000-0xdfff
[ 1.780050] pci 0000:00:1c.2: MEM window: 0xfb500000-0xfb5fffff
[ 1.780107] pci 0000:00:1c.2: PREFETCH window: 0x000000f4e00000-0x000000f4efffff
[ 1.780185] pci 0000:06:01.0: CardBus bridge, secondary bus 0000:07
[ 1.780240] pci 0000:06:01.0: IO window: 0x002000-0x0020ff
[ 1.780296] pci 0000:06:01.0: IO window: 0x002400-0x0024ff
[ 1.780353] pci 0000:06:01.0: PREFETCH window: 0xc0000000-0xc3ffffff
[ 1.780411] pci 0000:06:01.0: MEM window: 0xc8000000-0xcbffffff
[ 1.780468] pci 0000:00:1e.0: PCI bridge, secondary bus 0000:06
[ 1.780524] pci 0000:00:1e.0: IO window: 0x2000-0x2fff
[ 1.780580] pci 0000:00:1e.0: MEM window: 0xfb600000-0xfbefffff
[ 1.780637] pci 0000:00:1e.0: PREFETCH window: 0xc0000000-0xc3ffffff
[ 1.780701] pci 0000:00:01.0: setting latency timer to 64
[ 1.780708] pci 0000:00:03.0: setting latency timer to 64
[ 1.780714] pci 0000:00:07.0: setting latency timer to 64
[ 1.780720] pci 0000:00:1c.0: enabling device (0106 -> 0107)
[ 1.780778] pci 0000:00:1c.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
[ 1.780836] pci 0000:00:1c.0: setting latency timer to 64
[ 1.780843] pci 0000:00:1c.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[ 1.780901] pci 0000:00:1c.2: setting latency timer to 64
[ 1.780905] pci 0000:00:1e.0: setting latency timer to 64
[ 1.780913] pci 0000:06:01.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
[ 1.780972] pci_bus 0000:00: resource 0 io: [0x00-0xffff]
[ 1.780974] pci_bus 0000:00: resource 1 mem: [0x000000-0xffffffffffffffff]
[ 1.780976] pci_bus 0000:02: resource 0 io: [0xc000-0xcfff]
[ 1.780977] pci_bus 0000:02: resource 1 mem: [0xf8000000-0xfb4fffff]
[ 1.780979] pci_bus 0000:02: resource 2 pref mem [0xd0000000-0xdfffffff]
[ 1.780981] pci_bus 0000:05: resource 0 io: [0x1000-0x1fff]
[ 1.780982] pci_bus 0000:05: resource 1 mem: [0xc4000000-0xc41fffff]
[ 1.780984] pci_bus 0000:05: resource 2 pref mem [0xc4200000-0xc43fffff]
[ 1.780985] pci_bus 0000:04: resource 0 io: [0xd000-0xdfff]
[ 1.780987] pci_bus 0000:04: resource 1 mem: [0xfb500000-0xfb5fffff]
[ 1.780988] pci_bus 0000:04: resource 2 pref mem [0xf4e00000-0xf4efffff]
[ 1.780990] pci_bus 0000:06: resource 0 io: [0x2000-0x2fff]
[ 1.780992] pci_bus 0000:06: resource 1 mem: [0xfb600000-0xfbefffff]
[ 1.780993] pci_bus 0000:06: resource 2 pref mem [0xc0000000-0xc3ffffff]
[ 1.780995] pci_bus 0000:06: resource 3 io: [0x00-0xffff]
[ 1.780996] pci_bus 0000:06: resource 4 mem: [0x000000-0xffffffffffffffff]
[ 1.780998] pci_bus 0000:07: resource 0 io: [0x2000-0x20ff]
[ 1.780999] pci_bus 0000:07: resource 1 io: [0x2400-0x24ff]
[ 1.781001] pci_bus 0000:07: resource 2 pref mem [0xc0000000-0xc3ffffff]
[ 1.781002] pci_bus 0000:07: resource 3 mem: [0xc8000000-0xcbffffff]
[ 1.781025] NET: Registered protocol family 2
[ 1.781147] IP route cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 1.781738] TCP established hash table entries: 262144 (order: 10, 4194304 bytes)
[ 1.782392] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[ 1.782581] TCP: Hash tables configured (established 262144 bind 65536)
[ 1.782637] TCP reno registered
[ 1.782750] NET: Registered protocol family 1
[ 1.782949] pci 0000:02:00.0: Boot video device
[ 1.782987] Trying to unpack rootfs image as initramfs...
[ 1.910206] Freeing initrd memory: 7708k freed
[ 1.911618] Scanning for low memory corruption every 60 seconds
[ 1.911757] audit: initializing netlink socket (disabled)
[ 1.911819] type=2000 audit(1256463027.790:1): initialized
[ 1.915634] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 1.916649] VFS: Disk quotas dquot_6.5.2
[ 1.916738] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 1.917203] fuse init (API version 7.13)
[ 1.917306] msgmni has been set to 24021
[ 1.917549] alg: No test for stdrng (krng)
[ 1.917606] io scheduler noop registered
[ 1.917659] io scheduler anticipatory registered
[ 1.917711] io scheduler deadline registered
[ 1.917772] io scheduler cfq registered (default)
[ 1.917924] pcieport 0000:00:01.0: irq 48 for MSI/MSI-X
[ 1.917930] pcieport 0000:00:01.0: setting latency timer to 64
[ 1.918021] pcieport 0000:00:03.0: irq 49 for MSI/MSI-X
[ 1.918027] pcieport 0000:00:03.0: setting latency timer to 64
[ 1.918114] pcieport 0000:00:07.0: irq 50 for MSI/MSI-X
[ 1.918120] pcieport 0000:00:07.0: setting latency timer to 64
[ 1.918206] pcieport 0000:00:1c.0: irq 51 for MSI/MSI-X
[ 1.918212] pcieport 0000:00:1c.0: setting latency timer to 64
[ 1.918305] pcieport 0000:00:1c.2: irq 52 for MSI/MSI-X
[ 1.918312] pcieport 0000:00:1c.2: setting latency timer to 64
[ 1.918374] aer 0000:00:01.0:pcie02: AER service couldn't init device: no _OSC support
[ 1.918379] aer 0000:00:03.0:pcie02: AER service couldn't init device: no _OSC support
[ 1.918383] aer 0000:00:07.0:pcie02: AER service couldn't init device: no _OSC support
[ 1.918388] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[ 1.918500] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
[ 1.918643] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
[ 1.918716] ACPI: Power Button [PWRB]
[ 1.918793] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
[ 1.918863] ACPI: Power Button [PWRF]
[ 1.919601] ACPI: SSDT 00000000bf6980c0 00403 (v01 DpgPmm P001Ist 00000011 INTL 20060113)
[ 1.920135] ACPI: SSDT 00000000bf69a140 003B2 (v01 PmRef P001Cst 00003001 INTL 20060113)
[ 1.922757] Monitor-Mwait will be used to enter C-1 state
[ 1.922776] Monitor-Mwait will be used to enter C-2 state
[ 1.922795] Monitor-Mwait will be used to enter C-3 state
[ 1.922835] processor LNXCPU:00: registered as cooling_device0
[ 1.923280] ACPI: SSDT 00000000bf6984d0 00403 (v01 DpgPmm P002Ist 00000012 INTL 20060113)
[ 1.923746] ACPI: SSDT 00000000bf69a500 00085 (v01 PmRef P002Cst 00003000 INTL 20060113)
[ 1.926363] processor LNXCPU:01: registered as cooling_device1
[ 1.926817] ACPI: SSDT 00000000bf6988e0 00403 (v01 DpgPmm P003Ist 00000012 INTL 20060113)
[ 1.927291] ACPI: SSDT 00000000bf69a590 00085 (v01 PmRef P003Cst 00003000 INTL 20060113)
[ 1.929905] processor LNXCPU:02: registered as cooling_device2
[ 1.930364] ACPI: SSDT 00000000bf698cf0 00403 (v01 DpgPmm P004Ist 00000012 INTL 20060113)
[ 1.930841] ACPI: SSDT 00000000bf69a620 00085 (v01 PmRef P004Cst 00003000 INTL 20060113)
[ 1.933470] processor LNXCPU:03: registered as cooling_device3
[ 1.933919] ACPI: SSDT 00000000bf699100 00403 (v01 DpgPmm P005Ist 00000012 INTL 20060113)
[ 1.934387] ACPI: SSDT 00000000bf69a6b0 00085 (v01 PmRef P005Cst 00003000 INTL 20060113)
[ 1.937008] processor LNXCPU:04: registered as cooling_device4
[ 1.937465] ACPI: SSDT 00000000bf699510 00403 (v01 DpgPmm P006Ist 00000012 INTL 20060113)
[ 1.937944] ACPI: SSDT 00000000bf69a740 00085 (v01 PmRef P006Cst 00003000 INTL 20060113)
[ 1.940567] processor LNXCPU:05: registered as cooling_device5
[ 1.941029] ACPI: SSDT 00000000bf699920 00403 (v01 DpgPmm P007Ist 00000012 INTL 20060113)
[ 1.941510] ACPI: SSDT 00000000bf69a7d0 00085 (v01 PmRef P007Cst 00003000 INTL 20060113)
[ 1.944138] processor LNXCPU:06: registered as cooling_device6
[ 1.944587] ACPI: SSDT 00000000bf699d30 00403 (v01 DpgPmm P008Ist 00000012 INTL 20060113)
[ 1.945063] ACPI: SSDT 00000000bf69a860 00085 (v01 PmRef P008Cst 00003000 INTL 20060113)
[ 1.947693] processor LNXCPU:07: registered as cooling_device7
[ 1.950071] XENFS: not registering filesystem on non-xen platform
[ 1.950853] Linux agpgart interface v0.103
[ 1.950907] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 1.951754] brd: module loaded
[ 1.952076] loop: module loaded
[ 1.952170] input: Macintosh mouse button emulation as /devices/virtual/input/input2
[ 1.952326] ata_piix 0000:00:1f.2: version 2.13
[ 1.952340] ata_piix 0000:00:1f.2: PCI INT B -> GSI 20 (level, low) -> IRQ 20
[ 1.952399] ata_piix 0000:00:1f.2: MAP [ P0 P2 P1 P3 ]
[ 1.952630] ata_piix 0000:00:1f.2: setting latency timer to 64
[ 1.952668] scsi0 : ata_piix
[ 1.952762] scsi1 : ata_piix
[ 1.954017] ata1: SATA max UDMA/133 cmd 0xa000 ctl 0x9c00 bmdma 0x9480 irq 20
[ 1.954077] ata2: SATA max UDMA/133 cmd 0x9880 ctl 0x9800 bmdma 0x9488 irq 20
[ 1.954149] ata_piix 0000:00:1f.5: PCI INT B -> GSI 20 (level, low) -> IRQ 20
[ 1.954208] ata_piix 0000:00:1f.5: MAP [ P0 -- P1 -- ]
[ 1.954434] ata_piix 0000:00:1f.5: setting latency timer to 64
[ 1.954459] scsi2 : ata_piix
[ 1.954538] scsi3 : ata_piix
[ 1.955576] ata3: SATA max UDMA/133 cmd 0xb000 ctl 0xac00 bmdma 0xa480 irq 20
[ 1.955634] ata4: SATA max UDMA/133 cmd 0xa880 ctl 0xa800 bmdma 0xa488 irq 20
[ 1.956065] Fixed MDIO Bus: probed
[ 1.956117] PPP generic driver version 2.4.2
[ 1.956220] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 1.956288] ehci_hcd 0000:00:1a.7: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[ 1.956356] ehci_hcd 0000:00:1a.7: setting latency timer to 64
[ 1.956358] ehci_hcd 0000:00:1a.7: EHCI Host Controller
[ 1.956438] ehci_hcd 0000:00:1a.7: new USB bus registered, assigned bus number 1
[ 1.956526] ehci_hcd 0000:00:1a.7: debug port 1
[ 1.960454] ehci_hcd 0000:00:1a.7: cache line size of 32 is not supported
[ 1.960464] ehci_hcd 0000:00:1a.7: irq 18, io mem 0xf7fff000
[ 1.982777] ehci_hcd 0000:00:1a.7: USB 2.0 started, EHCI 1.00
[ 1.982889] usb usb1: configuration #1 chosen from 1 choice
[ 1.982959] hub 1-0:1.0: USB hub found
[ 1.983013] hub 1-0:1.0: 6 ports detected
[ 1.983109] ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 23 (level, low) -> IRQ 23
[ 1.983172] ehci_hcd 0000:00:1d.7: setting latency timer to 64
[ 1.983174] ehci_hcd 0000:00:1d.7: EHCI Host Controller
[ 1.983245] ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 2
[ 1.983331] ehci_hcd 0000:00:1d.7: debug port 1
[ 1.987268] ehci_hcd 0000:00:1d.7: cache line size of 32 is not supported
[ 1.987277] ehci_hcd 0000:00:1d.7: irq 23, io mem 0xf7ffe000
[ 2.012761] ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
[ 2.012867] usb usb2: configuration #1 chosen from 1 choice
[ 2.012936] hub 2-0:1.0: USB hub found
[ 2.012989] hub 2-0:1.0: 6 ports detected
[ 2.013078] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 2.013142] uhci_hcd: USB Universal Host Controller Interface driver
[ 2.013233] uhci_hcd 0000:00:1a.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[ 2.013293] uhci_hcd 0000:00:1a.0: setting latency timer to 64
[ 2.013296] uhci_hcd 0000:00:1a.0: UHCI Host Controller
[ 2.013369] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3
[ 2.013464] uhci_hcd 0000:00:1a.0: irq 16, io base 0x0000b800
[ 2.013567] usb usb3: configuration #1 chosen from 1 choice
[ 2.013635] hub 3-0:1.0: USB hub found
[ 2.013689] hub 3-0:1.0: 2 ports detected
[ 2.013771] uhci_hcd 0000:00:1a.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
[ 2.013831] uhci_hcd 0000:00:1a.1: setting latency timer to 64
[ 2.013833] uhci_hcd 0000:00:1a.1: UHCI Host Controller
[ 2.013904] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4
[ 2.013998] uhci_hcd 0000:00:1a.1: irq 21, io base 0x0000b880
[ 2.014097] usb usb4: configuration #1 chosen from 1 choice
[ 2.014166] hub 4-0:1.0: USB hub found
[ 2.014219] hub 4-0:1.0: 2 ports detected
[ 2.014300] uhci_hcd 0000:00:1a.2: PCI INT D -> GSI 19 (level, low) -> IRQ 19
[ 2.014359] uhci_hcd 0000:00:1a.2: setting latency timer to 64
[ 2.014362] uhci_hcd 0000:00:1a.2: UHCI Host Controller
[ 2.014431] uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5
[ 2.014525] uhci_hcd 0000:00:1a.2: irq 19, io base 0x0000bc00
[ 2.014625] usb usb5: configuration #1 chosen from 1 choice
[ 2.014693] hub 5-0:1.0: USB hub found
[ 2.014746] hub 5-0:1.0: 2 ports detected
[ 2.014828] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23
[ 2.014887] uhci_hcd 0000:00:1d.0: setting latency timer to 64
[ 2.014890] uhci_hcd 0000:00:1d.0: UHCI Host Controller
[ 2.014959] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6
[ 2.015048] uhci_hcd 0000:00:1d.0: irq 23, io base 0x0000b080
[ 2.015148] usb usb6: configuration #1 chosen from 1 choice
[ 2.015216] hub 6-0:1.0: USB hub found
[ 2.015270] hub 6-0:1.0: 2 ports detected
[ 2.015350] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19
[ 2.015409] uhci_hcd 0000:00:1d.1: setting latency timer to 64
[ 2.015412] uhci_hcd 0000:00:1d.1: UHCI Host Controller
[ 2.015481] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7
[ 2.016313] uhci_hcd 0000:00:1d.1: irq 19, io base 0x0000b400
[ 2.016414] usb usb7: configuration #1 chosen from 1 choice
[ 2.016481] hub 7-0:1.0: USB hub found
[ 2.016535] hub 7-0:1.0: 2 ports detected
[ 2.016616] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[ 2.016676] uhci_hcd 0000:00:1d.2: setting latency timer to 64
[ 2.016678] uhci_hcd 0000:00:1d.2: UHCI Host Controller
[ 2.016751] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8
[ 2.016839] uhci_hcd 0000:00:1d.2: irq 18, io base 0x0000b480
[ 2.016941] usb usb8: configuration #1 chosen from 1 choice
[ 2.017010] hub 8-0:1.0: USB hub found
[ 2.017063] hub 8-0:1.0: 2 ports detected
[ 2.017174] PNP: No PS/2 controller found. Probing ports directly.
[ 2.019657] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 2.019716] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 2.019812] mice: PS/2 mouse device common for all mice
[ 2.019908] Driver 'rtc_cmos' needs updating - please use bus_type methods
[ 2.019978] rtc_cmos 00:03: RTC can wake from S4
[ 2.020049] rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0
[ 2.020125] rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
[ 2.020264] device-mapper: uevent: version 1.0.3
[ 2.020365] device-mapper: ioctl: 4.15.0-ioctl (2009-04-01) initialised: dm-devel@redhat.com
[ 2.020528] device-mapper: multipath: version 1.1.0 loaded
[ 2.020592] device-mapper: multipath round-robin: version 1.0.0 loaded
[ 2.020986] cpuidle: using governor ladder
[ 2.021279] cpuidle: using governor menu
[ 2.021616] TCP cubic registered
[ 2.021747] NET: Registered protocol family 10
[ 2.022139] lo: Disabled Privacy Extensions
[ 2.022420] NET: Registered protocol family 17
[ 2.022485] Bluetooth: L2CAP ver 2.14
[ 2.022536] Bluetooth: L2CAP socket layer initialized
[ 2.022589] Bluetooth: SCO (Voice Link) ver 0.6
[ 2.022641] Bluetooth: SCO socket layer initialized
[ 2.022724] Bluetooth: RFCOMM TTY layer initialized
[ 2.022779] Bluetooth: RFCOMM socket layer initialized
[ 2.022832] Bluetooth: RFCOMM ver 1.11
[ 2.027721] PM: Resume from disk failed.
[ 2.027728] registered taskstats version 1
[ 2.028171] Magic number: 13:334:526
[ 2.028400] rtc_cmos 00:03: setting system clock to 2009-10-25 09:30:28 UTC (1256463028)
[ 2.028483] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
[ 2.028536] EDD information not available.
[ 2.309316] ata3: SATA link down (SStatus 0 SControl 300)
[ 2.458425] ata4: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 2.478769] ata4.00: ATA-7: SAMSUNG HD103UJ, 1AA01118, max UDMA7
[ 2.478831] ata4.00: 1953525168 sectors, multi 16: LBA48 NCQ (depth 0/32)
[ 2.498779] ata4.00: configured for UDMA/133
[ 2.518301] usb 3-2: new low speed USB device using uhci_hcd and address 2
[ 2.702445] usb 3-2: configuration #1 chosen from 1 choice
[ 2.808321] ata1.00: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 2.808338] ata2.00: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 2.808352] ata2.01: SATA link down (SStatus 0 SControl 300)
[ 2.808501] ata1.01: SATA link down (SStatus 0 SControl 300)
[ 2.808566] ata1.01: link offline, clearing class 3 to NONE
[ 2.828530] ata1.00: ATAPI: TSSTcorp CDDVDW SH-S223B, SB01, max UDMA/100
[ 2.828714] ata2.00: ATA-7: SAMSUNG HD154UI, 1AG01118, max UDMA7
[ 2.828770] ata2.00: 2930277168 sectors, multi 16: LBA48 NCQ (depth 0/32)
[ 2.848672] ata2.00: configured for UDMA/133
[ 2.868467] ata1.00: configured for UDMA/100
[ 2.869759] scsi 0:0:0:0: CD-ROM TSSTcorp CDDVDW SH-S223B SB01 PQ: 0 ANSI: 5
[ 2.873772] sr0: scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray
[ 2.873851] Uniform CD-ROM driver Revision: 3.20
[ 2.873968] sr 0:0:0:0: Attached scsi CD-ROM sr0
[ 2.873995] sr 0:0:0:0: Attached scsi generic sg0 type 5
[ 2.874262] scsi 1:0:0:0: Direct-Access ATA SAMSUNG HD154UI 1AG0 PQ: 0 ANSI: 5
[ 2.874507] sd 1:0:0:0: Attached scsi generic sg1 type 0
[ 2.874662] sd 1:0:0:0: [sda] 2930277168 512-byte logical blocks: (1.50 TB/1.36 TiB)
[ 2.874705] scsi 3:0:0:0: Direct-Access ATA SAMSUNG HD103UJ 1AA0 PQ: 0 ANSI: 5
[ 2.874770] sd 3:0:0:0: [sdb] 1953525168 512-byte logical blocks: (1.00 TB/931 GiB)
[ 2.874797] sd 3:0:0:0: [sdb] Write Protect is off
[ 2.874799] sd 3:0:0:0: [sdb] Mode Sense: 00 3a 00 00
[ 2.874813] sd 3:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 2.874885] sdb:
[ 2.874984] sd 3:0:0:0: Attached scsi generic sg2 type 0
[ 2.875149] sd 1:0:0:0: [sda] Write Protect is off
[ 2.875204] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.875218] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 2.875362] sda: sdb1 sdb2 < unknown partition table
[ 2.890305] sd 1:0:0:0: [sda] Attached SCSI disk
[ 2.911729] sdb5 >
[ 2.912126] sd 3:0:0:0: [sdb] Attached SCSI disk
[ 2.912295] Freeing unused kernel memory: 536k freed
[ 2.912414] Write protecting the kernel read-only data: 7548k
[ 2.983362] Floppy drive(s): fd0 is 1.44M
[ 2.989132] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
[ 2.989212] r8169 0000:04:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[ 2.989313] r8169 0000:04:00.0: setting latency timer to 64
[ 2.989364] r8169 0000:04:00.0: irq 53 for MSI/MSI-X
[ 2.989991] eth0: RTL8168c/8111c at 0xffffc9000007e000, 00:24:8c:a7:6e:2d, XID 1c4000c0 IRQ 53
[ 2.993449] usbcore: registered new interface driver hiddev
[ 3.012461] input: Cherry GmbH Cherry TouchBoard as /devices/pci0000:00/0000:00:1a.0/usb3/3-2/3-2:1.0/input/input3
[ 3.012582] generic-usb 0003:046A:002F.0001: input,hidraw0: USB HID v1.11 Keyboard [Cherry GmbH Cherry TouchBoard] on usb-0000:00:1a.0-2/input0
[ 3.013307] FDC 0 is a post-1991 82077
[ 3.037401] input: Cherry GmbH Cherry TouchBoard as /devices/pci0000:00/0000:00:1a.0/usb3/3-2/3-2:1.1/input/input4
[ 3.037518] generic-usb 0003:046A:002F.0002: input,hidraw1: USB HID v1.11 Mouse [Cherry GmbH Cherry TouchBoard] on usb-0000:00:1a.0-2/input1
[ 3.037609] usbcore: registered new interface driver usbhid
[ 3.037663] usbhid: v2.6:USB HID core driver
[ 4.152480] PM: Starting manual resume from disk
[ 4.152482] PM: Resume from partition 8:21
[ 4.152483] PM: Checking hibernation image.
[ 4.152687] PM: Resume from disk failed.
[ 4.169257] EXT4-fs (sdb1): INFO: recovery required on readonly filesystem
[ 4.169261] EXT4-fs (sdb1): write access will be enabled during recovery
[ 7.160195] EXT4-fs (sdb1): orphan cleanup on readonly fs
[ 7.160202] EXT4-fs (sdb1): ext4_orphan_cleanup: deleting unreferenced inode 34402
[ 7.175370] EXT4-fs (sdb1): 1 orphan inode deleted
[ 7.175375] EXT4-fs (sdb1): recovery complete
[ 8.170524] EXT4-fs (sdb1): mounted filesystem with ordered data mode
[ 11.013501] Adding 2000052k swap on /dev/sdb5. Priority:-1 extents:1 across:2000052k
[ 11.863971] SGI XFS with ACLs, security attributes, realtime, large block/inode numbers, no debug enabled
[ 11.866385] SGI XFS Quota Management subsystem
[ 11.911085] XFS mounting filesystem sda
[ 12.120549] Ending clean XFS mount for filesystem: sda
[ 12.634114] udev: starting version 147
[ 13.407398] yenta_cardbus 0000:06:01.0: CardBus bridge found [1524:1410]
[ 13.407415] yenta_cardbus 0000:06:01.0: Using CSCINT to route CSC interrupts to PCI
[ 13.407416] yenta_cardbus 0000:06:01.0: Routing CardBus interrupts to PCI
[ 13.407420] yenta_cardbus 0000:06:01.0: TI: mfunc 0x00001002, devctl 0x44
[ 13.655179] yenta_cardbus 0000:06:01.0: ISA IRQ mask 0x0000, PCI irq 17
[ 13.655182] yenta_cardbus 0000:06:01.0: Socket status: 30000020
[ 13.655184] pci_bus 0000:06: Raising subordinate bus# of parent bus (#06) from #07 to #0a
[ 13.655190] yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge I/O window: 0x2000 - 0x2fff
[ 13.655192] yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge Memory window: 0xfb600000 - 0xfbefffff
[ 13.655194] yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge Memory window: 0xc0000000 - 0xc3ffffff
[ 13.759239] cfg80211: Calling CRDA to update world regulatory domain
[ 14.137878] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 14.317377] pcmcia_socket pcmcia_socket0: pccard: CardBus card inserted into slot 0
[ 14.317406] pci 0000:07:00.0: reg 10 32bit mmio: [0x000000-0x00ffff]
[ 14.317468] yenta_cardbus 0000:06:01.0: EnE: chaning testregister 0xC9, 0e -> 0c
[ 14.429475] nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
[ 14.429712] CONFIG_NF_CT_ACCT is deprecated and will be removed soon. Please use
[ 14.429714] nf_conntrack.acct=1 kernel parameter, acct=1 nf_conntrack module option or
[ 14.429715] sysctl net.netfilter.nf_conntrack_acct=1 to enable it.
[ 14.503194] cfg80211: World regulatory domain updated:
[ 14.503196] (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[ 14.503198] (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[ 14.503200] (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[ 14.503201] (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[ 14.503203] (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[ 14.503204] (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[ 14.633928] rt61pci 0000:06:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[ 14.925570] RME Hammerfall DSP 0000:07:00.0: enabling device (0000 -> 0002)
[ 14.925578] RME Hammerfall DSP 0000:07:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
[ 14.939200] lp: driver loaded but no devices found
[ 15.029799] HDA Intel 0000:00:1b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
[ 15.029936] HDA Intel 0000:00:1b.0: setting latency timer to 64
[ 15.054844] phy0: Selected rate control algorithm 'minstrel'
[ 15.055434] Registered led device: rt61pci-phy0::radio
[ 15.055447] Registered led device: rt61pci-phy0::assoc
[ 15.065491] coretemp coretemp.0: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.065580] coretemp coretemp.1: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.065615] coretemp coretemp.2: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.065666] coretemp coretemp.3: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.065692] coretemp coretemp.4: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.065739] coretemp coretemp.5: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.065766] coretemp coretemp.6: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.065795] coretemp coretemp.7: Unable to access MSR 0xEE, for Tjmax, left at default
[ 15.134375] ip6_tables: (C) 2000-2006 Netfilter Core Team
[ 15.255251] hda_codec: ALC1200: BIOS auto-probing.
[ 17.208229] Hammerfall-DSP: wait for FIFO status <= 0 failed after 30 iterations
[ 17.208335] RME Hammerfall DSP 0000:07:00.0: firmware: requesting multiface_firmware_rev11.bin
[ 17.574666] Hammerfall-DSP: loading firmware
[ 18.406131] r8169: eth0: link down
[ 18.407119] ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 18.687322] rt61pci 0000:06:00.0: firmware: requesting rt2561.bin
[ 19.454112] ADDRCONF(NETDEV_UP): wlan0: link is not ready
[ 20.883755] Hammerfall-DSP: finished firmware loading
[ 54.689899] nvidia: module license 'NVIDIA' taints kernel.
[ 54.689902] Disabling lock debugging due to kernel taint
[ 55.163792] nvidia 0000:02:00.0: PCI INT A -> GSI 24 (level, low) -> IRQ 24
[ 55.163798] nvidia 0000:02:00.0: setting latency timer to 64
[ 55.164172] NVRM: loading NVIDIA UNIX x86_64 Kernel Module 185.18.36 Fri Aug 14 17:35:21 PDT 2009
[ 57.995198] ppdev: user-space parallel port driver
[ 60.858557] CPU0 attaching NULL sched-domain.
[ 60.858560] CPU1 attaching NULL sched-domain.
[ 60.858562] CPU2 attaching NULL sched-domain.
[ 60.858563] CPU3 attaching NULL sched-domain.
[ 60.858565] CPU4 attaching NULL sched-domain.
[ 60.858566] CPU5 attaching NULL sched-domain.
[ 60.858568] CPU6 attaching NULL sched-domain.
[ 60.858569] CPU7 attaching NULL sched-domain.
[ 60.961797] CPU0 attaching sched-domain:
[ 60.961800] domain 0: span 0,4 level SIBLING
[ 60.961801] groups: 0 (cpu_power = 589) 4 (cpu_power = 589)
[ 60.961805] domain 1: span 0-7 level MC
[ 60.961806] groups: 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178)
[ 60.961813] CPU1 attaching sched-domain:
[ 60.961814] domain 0: span 1,5 level SIBLING
[ 60.961815] groups: 1 (cpu_power = 589) 5 (cpu_power = 589)
[ 60.961818] domain 1: span 0-7 level MC
[ 60.961819] groups: 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178)
[ 60.961825] CPU2 attaching sched-domain:
[ 60.961826] domain 0: span 2,6 level SIBLING
[ 60.961827] groups: 2 (cpu_power = 589) 6 (cpu_power = 589)
[ 60.961830] domain 1: span 0-7 level MC
[ 60.961831] groups: 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178)
[ 60.961837] CPU3 attaching sched-domain:
[ 60.961838] domain 0: span 3,7 level SIBLING
[ 60.961839] groups: 3 (cpu_power = 589) 7 (cpu_power = 589)
[ 60.961842] domain 1: span 0-7 level MC
[ 60.961843] groups: 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178)
[ 60.961849] CPU4 attaching sched-domain:
[ 60.961850] domain 0: span 0,4 level SIBLING
[ 60.961851] groups: 4 (cpu_power = 589) 0 (cpu_power = 589)
[ 60.961854] domain 1: span 0-7 level MC
[ 60.961855] groups: 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178)
[ 60.961861] CPU5 attaching sched-domain:
[ 60.961862] domain 0: span 1,5 level SIBLING
[ 60.961863] groups: 5 (cpu_power = 589) 1 (cpu_power = 589)
[ 60.961866] domain 1: span 0-7 level MC
[ 60.961867] groups: 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178)
[ 60.961872] CPU6 attaching sched-domain:
[ 60.961873] domain 0: span 2,6 level SIBLING
[ 60.961875] groups: 6 (cpu_power = 589) 2 (cpu_power = 589)
[ 60.961878] domain 1: span 0-7 level MC
[ 60.961879] groups: 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178)
[ 60.961884] CPU7 attaching sched-domain:
[ 60.961885] domain 0: span 3,7 level SIBLING
[ 60.961886] groups: 7 (cpu_power = 589) 3 (cpu_power = 589)
[ 60.961889] domain 1: span 0-7 level MC
[ 60.961891] groups: 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178)
[ 62.534294] CPU0 attaching NULL sched-domain.
[ 62.534298] CPU1 attaching NULL sched-domain.
[ 62.534299] CPU2 attaching NULL sched-domain.
[ 62.534301] CPU3 attaching NULL sched-domain.
[ 62.534302] CPU4 attaching NULL sched-domain.
[ 62.534303] CPU5 attaching NULL sched-domain.
[ 62.534305] CPU6 attaching NULL sched-domain.
[ 62.534306] CPU7 attaching NULL sched-domain.
[ 62.611769] CPU0 attaching sched-domain:
[ 62.611774] domain 0: span 0,4 level SIBLING
[ 62.611777] groups: 0 (cpu_power = 589) 4 (cpu_power = 589)
[ 62.611783] domain 1: span 0-7 level MC
[ 62.611786] groups: 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178)
[ 62.611796] CPU1 attaching sched-domain:
[ 62.611798] domain 0: span 1,5 level SIBLING
[ 62.611801] groups: 1 (cpu_power = 589) 5 (cpu_power = 589)
[ 62.611806] domain 1: span 0-7 level MC
[ 62.611809] groups: 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178)
[ 62.611820] CPU2 attaching sched-domain:
[ 62.611821] domain 0: span 2,6 level SIBLING
[ 62.611822] groups: 2 (cpu_power = 589) 6 (cpu_power = 589)
[ 62.611825] domain 1: span 0-7 level MC
[ 62.611826] groups: 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178)
[ 62.611831] CPU3 attaching sched-domain:
[ 62.611833] domain 0: span 3,7 level SIBLING
[ 62.611834] groups: 3 (cpu_power = 589) 7 (cpu_power = 589)
[ 62.611837] domain 1: span 0-7 level MC
[ 62.611838] groups: 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178)
[ 62.611843] CPU4 attaching sched-domain:
[ 62.611844] domain 0: span 0,4 level SIBLING
[ 62.611846] groups: 4 (cpu_power = 589) 0 (cpu_power = 589)
[ 62.611849] domain 1: span 0-7 level MC
[ 62.611850] groups: 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178)
[ 62.611855] CPU5 attaching sched-domain:
[ 62.611856] domain 0: span 1,5 level SIBLING
[ 62.611857] groups: 5 (cpu_power = 589) 1 (cpu_power = 589)
[ 62.611860] domain 1: span 0-7 level MC
[ 62.611862] groups: 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178)
[ 62.611867] CPU6 attaching sched-domain:
[ 62.611868] domain 0: span 2,6 level SIBLING
[ 62.611869] groups: 6 (cpu_power = 589) 2 (cpu_power = 589)
[ 62.611872] domain 1: span 0-7 level MC
[ 62.611873] groups: 2,6 (cpu_power = 1178) 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178)
[ 62.611879] CPU7 attaching sched-domain:
[ 62.611880] domain 0: span 3,7 level SIBLING
[ 62.611881] groups: 7 (cpu_power = 589) 3 (cpu_power = 589)
[ 62.611884] domain 1: span 0-7 level MC
[ 62.611885] groups: 3,7 (cpu_power = 1178) 0,4 (cpu_power = 1178) 1,5 (cpu_power = 1178) 2,6 (cpu_power = 1178)
[ 161.465997] wlan0: deauthenticating from 00:14:6c:5a:96:60 by local choice (reason=3)
[ 161.466091] wlan0: direct probe to AP 00:14:6c:5a:96:60 (try 1)
[ 161.662769] wlan0: direct probe to AP 00:14:6c:5a:96:60 (try 2)
[ 161.862701] wlan0: direct probe to AP 00:14:6c:5a:96:60 (try 3)
[ 162.062642] wlan0: direct probe to AP 00:14:6c:5a:96:60 timed out
[ 167.834049] wlan0: deauthenticating from 00:14:6c:5a:96:60 by local choice (reason=3)
[ 167.853756] wlan0: direct probe to AP 00:24:fe:09:94:18 (try 1)
[ 167.855736] wlan0: direct probe responded
[ 167.855740] wlan0: authenticate with AP 00:24:fe:09:94:18 (try 1)
[ 167.857694] wlan0: authenticated
[ 167.857713] wlan0: associate with AP 00:24:fe:09:94:18 (try 1)
[ 167.860555] wlan0: RX AssocResp from 00:24:fe:09:94:18 (capab=0x401 status=0 aid=1)
[ 167.860558] wlan0: associated
[ 167.863330] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
[ 178.436829] wlan0: no IPv6 routers present
[ 370.891613] phy0 -> rt2x00queue_write_tx_frame: Error - Arrived at non-free entry in the non-full queue 2.
[ 370.891615] Please file bug report to http://rt2x00.serialmonkey.com.
[ 1704.723736] wlan0: deauthenticating from 00:24:fe:09:94:18 by local choice (reason=3)
[ 1704.723777] wlan0: deauthenticating from 00:24:fe:09:94:18 by local choice (reason=3)
[ 1704.743717] wlan0: direct probe to AP 00:14:6c:5a:96:60 (try 1)
[ 1704.780772] wlan0: direct probe responded
[ 1704.780777] wlan0: authenticate with AP 00:14:6c:5a:96:60 (try 1)
[ 1704.782663] wlan0: authenticated
[ 1704.805416] wlan0: associate with AP 00:14:6c:5a:96:60 (try 1)
[ 1704.807591] wlan0: RX ReassocResp from 00:14:6c:5a:96:60 (capab=0x401 status=0 aid=2)
[ 1704.807594] wlan0: associated
[ 1728.527813] wlan0: deauthenticated from 00:14:6c:5a:96:60 (Reason: 7)
[ 1730.094888] wlan0: direct probe to AP 00:14:6c:5a:96:60 (try 1)
[ 1730.096494] wlan0: direct probe responded
[ 1730.096498] wlan0: authenticate with AP 00:14:6c:5a:96:60 (try 1)
[ 1730.098433] wlan0: authenticated
[ 1730.098454] wlan0: associate with AP 00:14:6c:5a:96:60 (try 1)
[ 1730.294810] wlan0: associate with AP 00:14:6c:5a:96:60 (try 2)
[ 1730.298806] wlan0: RX ReassocResp from 00:14:6c:5a:96:60 (capab=0x401 status=0 aid=2)
[ 1730.298809] wlan0: associated
[ 1787.505633] wlan0: deauthenticated from 00:14:6c:5a:96:60 (Reason: 7)
[ 1789.074288] wlan0: direct probe to AP 00:14:6c:5a:96:60 (try 1)
[ 1789.075897] wlan0: direct probe responded
[ 1789.075901] wlan0: authenticate with AP 00:14:6c:5a:96:60 (try 1)
[ 1789.077971] wlan0: authenticated
[ 1789.077990] wlan0: associate with AP 00:14:6c:5a:96:60 (try 1)
[ 1789.080117] wlan0: RX ReassocResp from 00:14:6c:5a:96:60 (capab=0x401 status=0 aid=2)
[ 1789.080121] wlan0: associated
[ 1824.712469] wlan0: deauthenticating from 00:14:6c:5a:96:60 by local choice (reason=3)
[ 1824.712512] wlan0: direct probe to AP 00:14:6c:5a:96:60 (try 1)
[ 1824.712526] wlan0: deauthenticating from 00:14:6c:5a:96:60 by local choice (reason=3)
[ 1824.732454] wlan0: direct probe to AP 00:24:fe:09:94:18 (try 1)
[ 1824.734953] wlan0: direct probe responded
[ 1824.734958] wlan0: authenticate with AP 00:24:fe:09:94:18 (try 1)
[ 1824.738308] wlan0: authenticated
[ 1824.814189] wlan0: associate with AP 00:24:fe:09:94:18 (try 1)
[ 1824.816959] wlan0: RX ReassocResp from 00:24:fe:09:94:18 (capab=0x401 status=0 aid=1)
[ 1824.816963] wlan0: associated
[ 2112.943630] phy0 -> rt2x00queue_write_tx_frame: Error - Arrived at non-free entry in the non-full queue 2.
[ 2112.943632] Please file bug report to http://rt2x00.serialmonkey.com.
[ 2596.790597] sr 0:0:0:0: [sr0] unaligned transfer
[ 2596.790663] sr 0:0:0:0: [sr0] unaligned transfer
[ 2596.790720] sr 0:0:0:0: [sr0] unaligned transfer
[ 2596.790742] sr 0:0:0:0: [sr0] unaligned transfer
[ 2596.792563] sr 0:0:0:0: [sr0] Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE
[ 2596.792569] sr 0:0:0:0: [sr0] Sense Key : Illegal Request [current]
[ 2596.792574] sr 0:0:0:0: [sr0] Add. Sense: Illegal mode for this track
[ 2596.792580] sr 0:0:0:0: [sr0] CDB: Read(10): 28 00 00 00 00 00 00 00 02 00
[ 2596.792589] end_request: I/O error, dev sr0, sector 0
[ 2596.836252] sr 0:0:0:0: [sr0] Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE
[ 2596.836264] sr 0:0:0:0: [sr0] Sense Key : Illegal Request [current]
[ 2596.836277] sr 0:0:0:0: [sr0] Add. Sense: Illegal mode for this track
[ 2596.836294] sr 0:0:0:0: [sr0] CDB: Read(10): 28 00 00 00 00 00 00 00 02 00
[ 2596.836320] end_request: I/O error, dev sr0, sector 0
[ 2596.837812] sr 0:0:0:0: [sr0] Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE
[ 2596.837817] sr 0:0:0:0: [sr0] Sense Key : Illegal Request [current]
[ 2596.837822] sr 0:0:0:0: [sr0] Add. Sense: Illegal mode for this track
[ 2596.837827] sr 0:0:0:0: [sr0] CDB: Read(10): 28 00 00 00 00 00 00 00 02 00
[ 2596.837837] end_request: I/O error, dev sr0, sector 0
[ 2826.143822] wlan0: deauthenticating from 00:24:fe:09:94:18 by local choice (reason=3)
[ 2826.143939] wlan0: deauthenticating from 00:24:fe:09:94:18 by local choice (reason=3)
[ 2827.646318] phy0 -> rt61pci_wait_bbp_ready: Error - BBP register access failed, aborting.
[ 2827.646323] phy0 -> rt61pci_set_device_state: Error - Device failed to enter state 4 (-5).
[ 2873.143407] BUG: unable to handle kernel NULL pointer dereference at 0000000000000020
[ 2873.143413] IP: [<ffffffffa01e7290>] rt2x00pci_free_queue_dma+0x20/0xd0 [rt2x00pci]
[ 2873.143421] PGD 2dec1a067 PUD 26c1bc067 PMD 0
[ 2873.143426] Oops: 0000 [#1] PREEMPT SMP
[ 2873.143429] last sysfs file: /sys/devices/platform/coretemp.3/temp1_input
[ 2873.143433] CPU 0
[ 2873.143434] Modules linked in: binfmt_misc ppdev nvidia(P) ipt_REJECT ipt_LOG xt_limit xt_tcpudp xt_state ipt_addrtype snd_hda_codec_realtek ip6table_filter ip6_tables nf_nat_irc coretemp arc4 snd_hda_intel nf_conntrack_irc snd_hda_codec snd_hdsp nf_nat_ftp nf_nat nf_conntrack_ipv4 nf_defrag_ipv4 snd_pcm_oss rt61pci(-) crc_itu_t snd_mixer_oss nf_conntrack_ftp lp snd_pcm nf_conntrack rt2x00pci snd_hwdep parport iptable_filter rt2x00lib snd_seq_dummy snd_seq_oss snd_seq_midi ip_tables x_tables led_class snd_rawmidi snd_seq_midi_event snd_seq mac80211 snd_timer snd_seq_device cfg80211 eeprom_93cx6 snd psmouse pcmcia soundcore snd_page_alloc serio_raw yenta_socket rsrc_nonstatic pcmcia_core xfs exportfs usbhid r8169 mii floppy
[ 2873.143487] Pid: 4677, comm: rmmod Tainted: P 2.6.32-rc5 #35 System Product Name
[ 2873.143490] RIP: 0010:[<ffffffffa01e7290>] [<ffffffffa01e7290>] rt2x00pci_free_queue_dma+0x20/0xd0 [rt2x00pci]
[ 2873.143496] RSP: 0018:ffff880305e53cf8 EFLAGS: 00010282
[ 2873.143499] RAX: 0000000000000000 RBX: ffff8803312e51e0 RCX: 0000000000000000
[ 2873.143501] RDX: 0000000000000150 RSI: ffff880331290c00 RDI: ffff8803312e51e0
[ 2873.143504] RBP: ffff880305e53d38 R08: 0000000000000000 R09: 0000000000000000
[ 2873.143506] R10: 0000000000000001 R11: 0000000000000000 R12: ffff880331290c38
[ 2873.143508] R13: ffff8803312e4340 R14: ffff8803312e51e0 R15: 0000000000000001
[ 2873.143511] FS: 00007f4e38e146f0(0000) GS:ffff880028200000(0000) knlGS:0000000000000000
[ 2873.143514] CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b
[ 2873.143517] CR2: 0000000000000020 CR3: 00000002b2e66000 CR4: 00000000000006b0
[ 2873.143519] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 2873.143522] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
[ 2873.143525] Process rmmod (pid: 4677, threadinfo ffff880305e52000, task ffff880305f50000)
[ 2873.143527] Stack:
[ 2873.143528] ffff8803312e51e0 0000000000000001 ffff880305e53d38 ffff8803312e51e0
[ 2873.143532] <0> ffff880331290c38 ffff8803312e4340 ffff8803312e51e0 0000000000000001
[ 2873.143537] <0> ffff880305e53d58 ffffffffa01e7378 ffff8803312e51e0 ffff880333afc080
[ 2873.143542] Call Trace:
[ 2873.143548] [<ffffffffa01e7378>] rt2x00pci_uninitialize+0x38/0x70 [rt2x00pci]
[ 2873.143554] [<ffffffffa01c8062>] rt2x00lib_uninitialize+0x32/0x60 [rt2x00lib]
[ 2873.143560] [<ffffffffa01c886d>] rt2x00lib_remove_dev+0x2d/0xc0 [rt2x00lib]
[ 2873.143565] [<ffffffffa01e718c>] rt2x00pci_remove+0x3c/0x120 [rt2x00pci]
[ 2873.143572] [<ffffffff81298fbf>] pci_device_remove+0x2f/0x60
[ 2873.143578] [<ffffffff8132eec3>] __device_release_driver+0x53/0xb0
[ 2873.143582] [<ffffffff8132efe0>] driver_detach+0xc0/0xd0
[ 2873.143587] [<ffffffff8132df44>] bus_remove_driver+0x94/0xc0
[ 2873.143591] [<ffffffff8132f5a9>] driver_unregister+0x59/0x90
[ 2873.143595] [<ffffffff8129925f>] pci_unregister_driver+0x3f/0xb0
[ 2873.143601] [<ffffffffa024f290>] rt61pci_exit+0x10/0x12 [rt61pci]
[ 2873.143608] [<ffffffff810923f3>] sys_delete_module+0x183/0x250
[ 2873.143613] [<ffffffff8107dbe9>] ? up_read+0x9/0x10
[ 2873.143618] [<ffffffff815351df>] ? do_page_fault+0x13f/0x3f0
[ 2873.143624] [<ffffffff81011f02>] system_call_fastpath+0x16/0x1b
[ 2873.143627] Code: b8 ea ff ff ff eb b3 0f 1f 40 00 55 48 89 e5 48 83 ec 40 48 89 5d d8 4c 89 65 e0 4c 89 6d e8 4c 89 75 f0 4c 89 7d f8 48 8b 46 08 <48> 8b 58 20 48 8b 13 48 85 d2 74 4c 4c 8b 27 48 8b 4b 08 44 0f
[ 2873.143663] RIP [<ffffffffa01e7290>] rt2x00pci_free_queue_dma+0x20/0xd0 [rt2x00pci]
[ 2873.143669] RSP <ffff880305e53cf8>
[ 2873.143670] CR2: 0000000000000020
[ 2873.143673] ---[ end trace af6b473a456cf4f3 ]---
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [PATCH 17/19] [RFC, v2] libertas: Kconfig entry for libertas+cfg80211
From: Christoph Hellwig @ 2009-10-25 3:38 UTC (permalink / raw)
To: Dan Williams; +Cc: Holger Schurig, Johannes Berg, linux-wireless, John Linville
In-Reply-To: <1256315415.2164.46.camel@localhost.localdomain>
How much does mesh actually get used? AFAICS it's a OLPC-specific one
off. So unless OLPC people come up and fix it why do people even bother
with it?
^ permalink raw reply
* Re: Wrong BSSID generation in IBSS mode with ath5k
From: X Xiao @ 2009-10-25 0:18 UTC (permalink / raw)
To: Karol Pucyński, Nick Kossifidis; +Cc: linux-wireless
In-Reply-To: <40f31dec0910241627i5dec6d33g57af6a1104bce91c@mail.gmail.com>
there was a patch fixed that, it's on the list a few days back.
--- On Sat, 10/24/09, Nick Kossifidis <mickflemm@gmail.com> wrote:
> From: Nick Kossifidis <mickflemm@gmail.com>
> Subject: Re: Wrong BSSID generation in IBSS mode with ath5k
> To: "Karol Pucyński" <kpucynski@7bulls.com>
> Cc: linux-wireless@vger.kernel.org
> Date: Saturday, October 24, 2009, 6:27 PM
> 2009/10/20 Karol Pucyński <kpucynski@7bulls.com>:
> > Hi
> >
> > I have IBSS network (based on ath5k cards).
> > With the same channel/essid set cards often can't
> "negotiate" the
> > same BSSID. Two nodes beside each other both create
> new IBSS networks
> > and they are not trying to merge.
> > Workaround: forcing BSSID with iw does work.
> >
> > Do you know what can be the reason of this problem?
> >
> > Tested on 2.6.31 kernel. May be related to my earlier
> problem 'ath5k
> > IBSS fixed rate'...
> >
> > Best regards
> > --
> > Karol Pucyński
> > 7bulls.com Sp. z o.o.
> > kpucynski@7bulls.com
> >
>
> In my tests i had to force a scan on one of the cards (so
> that it
> knows what cells are active) and then set the essid. Does
> that work
> for you ?
>
> --
> GPG ID: 0xD21DB2DB
> As you read this post global entropy rises. Have Fun ;-)
> Nick
> --
> To unsubscribe from this list: send the line "unsubscribe
> linux-wireless" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: Wrong BSSID generation in IBSS mode with ath5k
From: Nick Kossifidis @ 2009-10-24 23:27 UTC (permalink / raw)
To: Karol Pucyński; +Cc: linux-wireless
In-Reply-To: <1256052469.6550.7.camel@kpucynski-laptop>
2009/10/20 Karol Pucyński <kpucynski@7bulls.com>:
> Hi
>
> I have IBSS network (based on ath5k cards).
> With the same channel/essid set cards often can't "negotiate" the
> same BSSID. Two nodes beside each other both create new IBSS networks
> and they are not trying to merge.
> Workaround: forcing BSSID with iw does work.
>
> Do you know what can be the reason of this problem?
>
> Tested on 2.6.31 kernel. May be related to my earlier problem 'ath5k
> IBSS fixed rate'...
>
> Best regards
> --
> Karol Pucyński
> 7bulls.com Sp. z o.o.
> kpucynski@7bulls.com
>
In my tests i had to force a scan on one of the cards (so that it
knows what cells are active) and then set the essid. Does that work
for you ?
--
GPG ID: 0xD21DB2DB
As you read this post global entropy rises. Have Fun ;-)
Nick
^ permalink raw reply
* Re: "Reserved instruction in kernel code" on ath9k insertion
From: Tomasz Chmielewski @ 2009-10-24 20:58 UTC (permalink / raw)
To: Larry Finger; +Cc: linux-wireless
In-Reply-To: <4AE36884.6060806@lwfinger.net>
Larry Finger schrieb:
>> # modprobe ath9k
>> [ 165.440000] Reserved instruction in kernel code[#1]:
(...)
>> [ 165.440000] Code: 00000000 00000000 00000000 <00003009> 005196a8
>> 005196a8 00000002 00000000 005166b0
>> [ 165.440000] Disabling lock debugging due to kernel taint
>> Segmentation fault
>> #
>
> Is that the start of the error dump?
Yes - as I do "modprobe", it starts to print the dump.
Then, modprobe segfaults.
> A BUG() statement places an
> illegal instruction in the code. Is that the case here?
I have no idea.
--
Tomasz Chmielewski
http://wpkg.org
^ permalink raw reply
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