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From: "Russell McGuire" <rmcguire@videopresence.com>
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Subject: RE: Audigy SE / ca0106 driver for PowerPC?
Date: Wed, 31 Jan 2007 15:42:58 -0800
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/* Configure PCI Local Access Windows  */
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;

pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;

-Russ

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org] 
Sent: Wednesday, January 31, 2007 3:19 PM
To: rmcguire@videopresence.com
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Audigy SE / ca0106 driver for PowerPC?


On Jan 31, 2007, at 5:01 PM, Russell McGuire wrote:

>
> What I really don't know is what the first column in the ranges  
> field does.
> I.e. the <42000000>, <02000000>, and <01000000>.

They are encoding of type of "space" is being described, the first  
byte's what's important:

[42]	- prefetchable memory
[02]	- 32-bit memory space
[01]	- IO space

[00]	- CFG space
[03]	- 64-bit memory space

> Here is part of current blob I am using:
>
> pci@8500 {
> 	linux,phandle = <8500>;
> 	interrupt-map-mask = <f800 0 0 7>;
> 	interrupt-map= <
>  		/* IDSEL 0x19 AD25*/
> 		 c800 0 0 1 700 14 8
> 		 c800 0 0 2 700 15 8
> 		 c800 0 0 3 700 16 8
> 		 c800 0 0 4 700 17 8>; > //and a lot more like this
> 	bus-range = <0 0>; //U-boot modifies this to be <0 2> I think
> 	ranges = <42000000 0 80000000 80000000 0 10000000
> 		  02000000 0 90000000 90000000 0 10000000
> 		  01000000 0 00000000 f0300000 0 00100000>;
> 	clock-frequency = <3f940aa>;
> 	#interrupt-cells = <1>;
> 	#size-cells = <2>;
> 	#address-cells = <3>;
> 	reg = <8500 100>;
> 	compatible = "83xx";
> 	device_type = "pci";
> }
>
> Here are the U-boot #defines I am using at the moment.
>
> #define CFG_PCI_MEM_BASE	0x80000000
> #define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
> #define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
> #define CFG_PCI_MMIO_BASE	0x90000000
> #define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
> #define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
> #define CFG_PCI_IO_BASE		0x00000000
> #define CFG_PCI_IO_PHYS		0xF0300000
> #define CFG_PCI_IO_SIZE		0x00100000 /* 1M */
> Might need to change PCI_IO_BASE to match PCI_IO_PHYS as well?

This all looks correct, how are you setting PCILAWBAR0/1, PCILAWAR0/1?

- k