From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id EFC65B708B for ; Sat, 18 Jul 2009 23:03:25 +1000 (EST) Received: from wf-out-1314.google.com (wf-out-1314.google.com [209.85.200.175]) by ozlabs.org (Postfix) with ESMTP id 0ADE7DDD01 for ; Sat, 18 Jul 2009 23:03:24 +1000 (EST) Received: by wf-out-1314.google.com with SMTP id 24so434229wfg.15 for ; Sat, 18 Jul 2009 06:03:22 -0700 (PDT) From: "Li Jun (Aaron)" To: Subject: how do linux active the ppc405 cache? Date: Sat, 18 Jul 2009 20:55:31 +0800 Message-ID: <001701ca07a7$0ba86a80$22f93f80$@com> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0018_01CA07EA.19CBAA80" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. ------=_NextPart_000_0018_01CA07EA.19CBAA80 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi all, I have a question about cache activation on the Xilinx Virtex4 ML403 board. I know that PowerPC instruction and data caches have to be activated manually with the command XCache_EnableICache(); XCache_EnableDCache(); It works well with the standalone application, but how about it in Linux system? When porting a linux 2.6 on the board, how the cache can be activated by the OS? Thanks ------=_NextPart_000_0018_01CA07EA.19CBAA80 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi all,

I have a question about cache activation on the Xilinx Virtex4 ML403 = board.

I know that PowerPC instruction and data caches have to be activated manually with the command

XCache_EnableICache();

XCache_EnableDCache();

It works well with the standalone application, but how about it in = Linux system?

 When porting a linux 2.6 on the board, how the  cache can = be activated by the OS?

Thanks

 

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