From mboxrd@z Thu Jan  1 00:00:00 1970
Reply-To: <lourens@mecalc.co.za>
From: "LC Geldenhuys" <lourens@mecalc.co.za>
To: <linuxppc-embedded@lists.linuxppc.org>
Subject: RE: Kernel Mode Software Emulation NIP: 00001FFC - cache coherency problem on m8xx processors
Date: Fri, 26 Mar 2004 09:23:52 +0200
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> -----Original Message-----
> From: owner-linuxppc-embedded@lists.linuxppc.org
> [mailto:owner-linuxppc-embedded@lists.linuxppc.org] On Behalf
> Of Marcelo Tosatti
> Sent: 26 March 2004 01:14 AM
> To: linuxppc-embedded@lists.linuxppc.org
> Subject: Kernel Mode Software Emulation NIP: 00001FFC - cache
> coherency problem on m8xx processors

<snip>

> I'm not exactly sure why we were jumping to "1FFC" instead of "2000",
> but adding "isync" before "bl transfer_to_handler" in both
> DecrementTimer
> and HardwareInterrupt fixed the problem for us.

This sounds distinctly familiar to the CPU13 Errata. Do you have
Instruction fetch show cycles enabled in ICTRL[IST_SER]? See:
http://e-www.motorola.com/files/32bit/doc/errata/MPC860CE.pdf

Cheers,
  Lourens


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