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[110.175.254.242]) by smtp.googlemail.com with ESMTPSA id x10-20020a170902ec8a00b0016cf195eb16sm524173plg.185.2022.08.11.21.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 21:22:31 -0700 (PDT) Message-ID: <0029908b1bf7b098b6b0ed2a129730a5313a7a37.camel@gmail.com> Subject: Re: [PATCH 12/17] powerpc/qspinlock: add ability to prod new queue head CPU From: Jordan Niethe To: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org Date: Fri, 12 Aug 2022 14:22:28 +1000 In-Reply-To: <20220728063120.2867508-14-npiggin@gmail.com> References: <20220728063120.2867508-1-npiggin@gmail.com> <20220728063120.2867508-14-npiggin@gmail.com> Content-Type: text/plain; charset="UTF-7" User-Agent: Evolution 3.36.5-0ubuntu1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, 2022-07-28 at 16:31 +-1000, Nicholas Piggin wrote: +AD4 After the head of the queue acquires the lock, it releases the +AD4 next waiter in the queue to become the new head. Add an option +AD4 to prod the new head if its vCPU was preempted. This may only +AD4 have an effect if queue waiters are yielding. +AD4 +AD4 Disable this option by default for now, i.e., no logical change. +AD4 --- +AD4 arch/powerpc/lib/qspinlock.c +AHw 29 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-- +AD4 1 file changed, 28 insertions(+-), 1 deletion(-) +AD4 +AD4 diff --git a/arch/powerpc/lib/qspinlock.c b/arch/powerpc/lib/qspinlock.c +AD4 index 28c85a2d5635..3b10e31bcf0a 100644 +AD4 --- a/arch/powerpc/lib/qspinlock.c +AD4 +-+-+- b/arch/powerpc/lib/qspinlock.c +AD4 +AEAAQA -12,6 +-12,7 +AEAAQA +AD4 struct qnode +AHs +AD4 struct qnode +ACo-next+ADs +AD4 struct qspinlock +ACo-lock+ADs +AD4 +- int cpu+ADs +AD4 int yield+AF8-cpu+ADs +AD4 u8 locked+ADs /+ACo 1 if lock acquired +ACo-/ +AD4 +AH0AOw +AD4 +AEAAQA -30,6 +-31,7 +AEAAQA static bool pv+AF8-yield+AF8-owner +AF8AXw-read+AF8-mostly +AD0 true+ADs +AD4 static bool pv+AF8-yield+AF8-allow+AF8-steal +AF8AXw-read+AF8-mostly +AD0 false+ADs +AD4 static bool pv+AF8-yield+AF8-prev +AF8AXw-read+AF8-mostly +AD0 true+ADs +AD4 static bool pv+AF8-yield+AF8-propagate+AF8-owner +AF8AXw-read+AF8-mostly +AD0 true+ADs +AD4 +-static bool pv+AF8-prod+AF8-head +AF8AXw-read+AF8-mostly +AD0 false+ADs +AD4 +AD4 static DEFINE+AF8-PER+AF8-CPU+AF8-ALIGNED(struct qnodes, qnodes)+ADs +AD4 +AD4 +AEAAQA -392,6 +-394,7 +AEAAQA static +AF8AXw-always+AF8-inline void queued+AF8-spin+AF8-lock+AF8-mcs+AF8-queue(struct qspinlock +ACo-lock, b +AD4 node +AD0 +ACY-qnodesp-+AD4-nodes+AFs-idx+AF0AOw +AD4 node-+AD4-next +AD0 NULL+ADs +AD4 node-+AD4-lock +AD0 lock+ADs +AD4 +- node-+AD4-cpu +AD0 smp+AF8-processor+AF8-id()+ADs I suppose this could be used in some other places too. For example change: yield+AF8-to+AF8-prev(lock, node, prev, paravirt)+ADs In yield+AF8-to+AF8-prev() it could then access the prev-+AD4-cpu. +AD4 node-+AD4-yield+AF8-cpu +AD0 -1+ADs +AD4 node-+AD4-locked +AD0 0+ADs +AD4 +AD4 +AEAAQA -483,7 +-486,14 +AEAAQA static +AF8AXw-always+AF8-inline void queued+AF8-spin+AF8-lock+AF8-mcs+AF8-queue(struct qspinlock +ACo-lock, b +AD4 +ACo this store to locked. The corresponding barrier is the smp+AF8-rmb() +AD4 +ACo acquire barrier for mcs lock, above. +AD4 +ACo-/ +AD4 - WRITE+AF8-ONCE(next-+AD4-locked, 1)+ADs +AD4 +- if (paravirt +ACYAJg pv+AF8-prod+AF8-head) +AHs +AD4 +- int next+AF8-cpu +AD0 next-+AD4-cpu+ADs +AD4 +- WRITE+AF8-ONCE(next-+AD4-locked, 1)+ADs +AD4 +- if (vcpu+AF8-is+AF8-preempted(next+AF8-cpu)) +AD4 +- prod+AF8-cpu(next+AF8-cpu)+ADs +AD4 +- +AH0 else +AHs +AD4 +- WRITE+AF8-ONCE(next-+AD4-locked, 1)+ADs +AD4 +- +AH0 +AD4 +AD4 release: +AD4 qnodesp-+AD4-count--+ADs /+ACo release the node +ACo-/ +AD4 +AEAAQA -622,6 +-632,22 +AEAAQA static int pv+AF8-yield+AF8-propagate+AF8-owner+AF8-get(void +ACo-data, u64 +ACo-val) +AD4 +AD4 DEFINE+AF8-SIMPLE+AF8-ATTRIBUTE(fops+AF8-pv+AF8-yield+AF8-propagate+AF8-owner, pv+AF8-yield+AF8-propagate+AF8-owner+AF8-get, pv+AF8-yield+AF8-propagate+AF8-owner+AF8-set, +ACIAJQ-llu+AFw-n+ACI)+ADs +AD4 +AD4 +-static int pv+AF8-prod+AF8-head+AF8-set(void +ACo-data, u64 val) +AD4 +-+AHs +AD4 +- pv+AF8-prod+AF8-head +AD0 +ACEAIQ-val+ADs +AD4 +- +AD4 +- return 0+ADs +AD4 +-+AH0 +AD4 +- +AD4 +-static int pv+AF8-prod+AF8-head+AF8-get(void +ACo-data, u64 +ACo-val) +AD4 +-+AHs +AD4 +- +ACo-val +AD0 pv+AF8-prod+AF8-head+ADs +AD4 +- +AD4 +- return 0+ADs +AD4 +-+AH0 +AD4 +- +AD4 +-DEFINE+AF8-SIMPLE+AF8-ATTRIBUTE(fops+AF8-pv+AF8-prod+AF8-head, pv+AF8-prod+AF8-head+AF8-get, pv+AF8-prod+AF8-head+AF8-set, +ACIAJQ-llu+AFw-n+ACI)+ADs +AD4 +- +AD4 static +AF8AXw-init int spinlock+AF8-debugfs+AF8-init(void) +AD4 +AHs +AD4 debugfs+AF8-create+AF8-file(+ACI-qspl+AF8-steal+AF8-spins+ACI, 0600, arch+AF8-debugfs+AF8-dir, NULL, +ACY-fops+AF8-steal+AF8-spins)+ADs +AD4 +AEAAQA -631,6 +-657,7 +AEAAQA static +AF8AXw-init int spinlock+AF8-debugfs+AF8-init(void) +AD4 debugfs+AF8-create+AF8-file(+ACI-qspl+AF8-pv+AF8-yield+AF8-allow+AF8-steal+ACI, 0600, arch+AF8-debugfs+AF8-dir, NULL, +ACY-fops+AF8-pv+AF8-yield+AF8-allow+AF8-steal)+ADs +AD4 debugfs+AF8-create+AF8-file(+ACI-qspl+AF8-pv+AF8-yield+AF8-prev+ACI, 0600, arch+AF8-debugfs+AF8-dir, NULL, +ACY-fops+AF8-pv+AF8-yield+AF8-prev)+ADs +AD4 debugfs+AF8-create+AF8-file(+ACI-qspl+AF8-pv+AF8-yield+AF8-propagate+AF8-owner+ACI, 0600, arch+AF8-debugfs+AF8-dir, NULL, +ACY-fops+AF8-pv+AF8-yield+AF8-propagate+AF8-owner)+ADs +AD4 +- debugfs+AF8-create+AF8-file(+ACI-qspl+AF8-pv+AF8-prod+AF8-head+ACI, 0600, arch+AF8-debugfs+AF8-dir, NULL, +ACY-fops+AF8-pv+AF8-prod+AF8-head)+ADs +AD4 +AH0 +AD4 +AD4 return 0+ADs