JTAG debug mechanism

JTAG debug mechanism

[Li Yang-r58472]

Hi,

I know this question is off topic, but I can't find a better place to ask.  I will be grateful if anyone can give me a hint or direct me to a reference.

As we know PowerPC use JTAG to debug CPU, which implements a Boundary-Scan mechanism.  It can manipulate any input/output signals of the CPU by a serial shift/scan process.  But my question is how it can read/write the core registers and system memory as implemented by most JTAG emulators.

Thanks,
Leo

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Re: JTAG debug mechanism

[Dan Malek]

On Aug 13, 2004, at 1:44 AM, Li Yang-r58472 wrote:

> .... But my question is how it can read/write the core registers and
> system memory as implemented by most JTAG emulators.

By using the Freescale COP implementation over the JTAG pins.
All debuggers do this.  Most of us don't care about such details,
we just buy the tools, plug them in and use them.


	-- Dan


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Re: JTAG debug mechanism

[Song Sam]

Li Yang-r58472 <LeoLi@freescale.com> wrote:

> As we know PowerPC use JTAG to debug CPU, which

But 8xx use BDM to debug CPU.So I wonder in which
situation or chips should we use BDM and JATG and
WHY??? For a embedded developer,he could more concern
about this point than JATG implementation process,I
guess.:-)

> implements a Boundary-Scan mechanism. It can manipulate any
> input/output signals of the CPU by a serial shift/scan process. But my
> question is how it can read/write the core registers and system memory
> as implemented by most JTAG emulators.

Any input is warmly welcome!

Best regards,

Sam

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Re: JTAG debug mechanism

[Mark Chambers]

>
> But 8xx use BDM to debug CPU.So I wonder in which
> situation or chips should we use BDM and JATG and
> WHY??? For a embedded developer,he could more concern
> about this point than JATG implementation process,I
> guess.:-)
>

As I think you know, JTAG and Boundary Scan are industry standards intended
primarily for
board manufacturing purposes.  Boundary Scan allows you access to the pins
on BGAs and other impossible-
to-reach pins on dense boards.  The Motorola CPUs simply borrow these same
pins for debug purposes, but
the internal debug logic is not directly related to JTAG.

Motorola does not release all the information about the debug interface on
all their processors.  However, the
BDM interface is well documented, and there is an open source project called
bdm4gdb.sourceforge.net, which
has the raw material for you to learn all you could want to know about bdm.

Good luck,
Mark Chambers


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Re: JTAG debug mechanism

[Wolfgang Denk]

In message <004301c48145$a072a150$0301a8c0@chuck2> you wrote:
>
> Motorola does not release all the information about the debug interface on
> all their processors.  However, the

Well, they do (or it would be impossible to build  devices  like  the
BDI2000), but only under NDA.

> BDM interface is well documented, and there is an open source project called
> bdm4gdb.sourceforge.net, which

...and this NDA also prevents us from implementing  COP  support  for
BDM4GDB  [at  least when basing the software on GDB which requires it
to be GPLed] :-(

Best regards,

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
Heavier than air flying machines are impossible.
                    -- Lord Kelvin, President, Royal Society, c. 1895

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Re: JTAG debug mechanism

[Song Sam]

Mark Chambers <markc@mail.com> wrote£º

> Motorola does not release all the information about the debug
> interface on all their processors. However, the BDM interface
> is well documented, and there is an open source project called
> bdm4gdb.sourceforge.net, which has the raw material for you to learn
> all you could want to know about bdm.

Thanks for giving this info.I enjoy it. :-)

Sam

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