From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from opnet2.opnet.com.tw (unknown [210.243.240.244]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id BA94867A6D for ; Fri, 17 Jun 2005 18:08:24 +1000 (EST) Message-ID: <006901c57313$9f6bc460$a40e000a@RoberHsu> From: =?big5?B?rn2z06vC?= To: Date: Fri, 17 Jun 2005 16:07:27 +0800 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0066_01C57356.A7E4F970" Cc: R64382@freescale.com, HHPPC Support Subject: Does any body have HYNIX or AMIC 32M SDRAM reference cdoe? List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. ------=_NextPart_000_0066_01C57356.A7E4F970 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: quoted-printable Hi All: I used HY57641620 * 2 total all 16M SDRAM at my MPC852T board, = now i want to=20 used HY57V281620ET-H * 2 or AMIC A43L3616-6 * 2 total all 32M SDRAM, = but i don't know how to setting UPM to control it, i need help.If you used another 32M = SDRAM solution, please tell me, thanks. #define _NOT_USED_ 0xFFFFFFFF const uint sdram_table[] =3D /* for HY57641620 * 2 16M SDRAM */ { /* Single Read. (offset 0x0-0x4 in UPM RAM) */ /* Precharge and MRS(offset 0x5-0x7 in UPM RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* Burst Read. (offset 0x8-0xf in UPM RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* Single Write. (offset 0x18-0x1F in UPM RAM) */ 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* Burst Write. (offset 20-2F in UPM RAM) */ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* Refresh timer expired (offset 30-3B in UPM RAM) */ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, 0xffffffff, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* Exception. (offset 3c-3f in UPM RAM) */ 0x7FFFFC07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; long int initdram(int board_type) { volatile immap_t *immap =3D (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl =3D &immap->im_memctl; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); =20 memctl->memc_mptpr =3D 0x0400; /* * Configure the refresh (mostly). This needs to be * based upon processor clock speed and optimized to provide * the highest level of performance. For multiple banks, * this time has to be divided by the number of banks. * Although it is not clear anywhere, it appears the * refresh steps through the chip selects for this UPM * on each refresh cycle. * We have to be careful changing * UPM registers after we ask it to run these commands. */ memctl->memc_mamr =3D 0xD0904114; memctl->memc_mar =3D 0x00000088; udelay(200); memctl->memc_mcr =3D 0x80004105; /* precharge */ udelay(200); memctl->memc_mamr =3D 0xD0904114; memctl->memc_mcr =3D 0x80004830; /* refresh */ udelay(200); memctl->memc_mamr =3D 0xD0904114; memctl->memc_mcr =3D 0x80004106;=20 udelay(200); memctl->memc_or2 =3D 0xFE000A00; memctl->memc_br2 =3D 0x00000081; return (32 * 1024 *1024); } /* end of initdram */ =20 ------=_NextPart_000_0066_01C57356.A7E4F970 Content-Type: text/html; charset="big5" Content-Transfer-Encoding: quoted-printable
Hi All:
 
       I used = HY57641620 * 2 total all 16M SDRAM at my MPC852T board, now i = want to=20
used HY57V281620ET-H * 2 or AMIC A43L3616-6 * 2 total = all =20 32M SDRAM, but i don't know
how to setting UPM to control it, i need help.If you used = another 32M=20 SDRAM solution,
please tell me, thanks.
 
 
#define _NOT_USED_      = 0xFFFFFFFF

const=20 uint sdram_table[] =3D   /* for HY57641620 * 2 16M  SDRAM = */
{
        /* Single Read. = (offset=20 0x0-0x4 in UPM RAM)    =20 */
        /* Precharge and = MRS(offset=20 0x5-0x7 in UPM RAM) */
        = 0x1F07FC04,=20 0xEEAEFC04, 0x11ADFC04,=20 0xEFBBBC00,
        0x1FF77C47,=20 0x1FF77C35, 0xEFEABC34,=20 0x1FB57C35,

        /* Burst = Read.=20 (offset 0x8-0xf in UPM RAM) = */
       =20 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04,=20 0xF0AFFC00,
        0xF0AFFC00,=20 0xF1AFFC00, 0xEFBBBC00,=20 0x1FF77C47,
        _NOT_USED_,=20 _NOT_USED_, _NOT_USED_,=20 _NOT_USED_,
        _NOT_USED_,=20 _NOT_USED_, _NOT_USED_,=20 _NOT_USED_,

        /* Single = Write.=20 (offset 0x18-0x1F in UPM RAM) = */
       =20 0x1F27FC04, 0xEEAEBC00, 0x01B93C04,=20 0x1FF77C47,
        _NOT_USED_,=20 _NOT_USED_, _NOT_USED_,=20 _NOT_USED_,

        /* Burst = Write.=20 (offset 20-2F in UPM RAM) = */
       =20 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00,=20 0xF0AFFC00,
        0xF0AFFC00,=20 0xE1BBBC04, 0x1FF77C47,=20 _NOT_USED_,
        _NOT_USED_,=20 _NOT_USED_, _NOT_USED_,=20 _NOT_USED_,
        _NOT_USED_,=20 _NOT_USED_, _NOT_USED_,=20 _NOT_USED_,

        /* Refresh = timer=20 expired (offset 30-3B in UPM RAM)=20 */
        0x1FF5FC84, 0xFFFFFC04, = 0xFFFFFC04, 0xFFFFFC04,
       =20 0xFFFFFC84, 0xFFFFFC07, 0xffffffff,=20 _NOT_USED_,
        _NOT_USED_,=20 _NOT_USED_, _NOT_USED_,=20 _NOT_USED_,

        /* = Exception.=20 (offset 3c-3f in UPM RAM) = */
       =20 0x7FFFFC07, _NOT_USED_, _NOT_USED_, _NOT_USED_
};
 
long int initdram(int = board_type)
{
 volatile=20 immap_t     *immap =3D (immap_t = *)CFG_IMMR;
 volatile=20 memctl8xx_t *memctl =3D &immap->im_memctl;
 
 upmconfig(UPMA, (uint *)sdram_table,=20 sizeof(sdram_table)/sizeof(uint));
  =
 memctl->memc_mptpr =3D=20 0x0400;
 
 /*
  * Configure the refresh = (mostly). =20 This needs to be
  * based upon processor clock speed and = optimized to=20 provide
  * the highest level of performance.  For multiple = banks,
  * this time has to be divided by the number of = banks.
 =20 * Although it is not clear anywhere, it appears the
  * refresh = steps=20 through the chip selects for this UPM
  * on each refresh=20 cycle.
  * We have to be careful changing
  * UPM = registers=20 after we ask it to run these commands.
  */
 
 memctl->memc_mamr =3D=20 0xD0904114;
 memctl->memc_mar =3D=20 0x00000088;
 udelay(200);
 
 memctl->memc_mcr =3D=20 0x80004105;     /* precharge=20 */
 udelay(200);
 
 memctl->memc_mamr =3D=20 0xD0904114;
 memctl->memc_mcr =3D = 0x80004830;    =20 /* refresh */
 udelay(200);
 
 memctl->memc_mamr =3D=20 0xD0904114;
 memctl->memc_mcr =3D 0x80004106;=20
 udelay(200);
 
 memctl->memc_or2 =3D=20 0xFE000A00;
 memctl->memc_br2 =3D 0x00000081;
 
 return (32 * 1024 *1024);
} /* end of = initdram=20 */

 
 
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