Ethernets on SCC2 and SCC3 on mpc8xx

Ethernets on SCC2 and SCC3 on mpc8xx

[Jan Damborsky]

Hello,

we want to use our custom board with MPC823e as
easy firewall in our applications. We have two 10Mbit ethernet
on board connected to SCC2 and SCC3 channels.
Is it support in kernel
for using both SCC channels configured as ethernet
(eth0, eth1 devices) simultaneously ? I use 2.4.3 kernel
and there is only possibility to use SCC2 or SCC3
as ethernet, not both at the same time.

                          Thanks in advance, HANYS


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Ethernets on SCC2 and SCC3 on mpc8xx

[Jan Damborsky]

Hello,

we want to use our custom board with MPC823e as
easy firewall in our applications. We have two 10Mbit ethernet
on board connected to SCC2 and SCC3 channels.
Is it support in kernel
for using both SCC channels configured as ethernet
(eth0, eth1 devices) simultaneously ? I use 2.4.3 kernel
and there is only possibility to use SCC2 or SCC3
as ethernet, not both at the same time.

                           Thanks in advance, HANYS


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Ethernets on SCC2 and SCC3 on mpc8xx

[Jan Damborsky]

Hello,

we want to use our custom board with MPC823e as
easy firewall in our applications. We have two 10Mbit ethernet
on board connected to SCC2 and SCC3 channels.
Is it support in kernel
for using both SCC channels configured as ethernet
(eth0, eth1 devices) simultaneously ? I use 2.4.3 kernel
and there is only possibility to use SCC2 or SCC3
as ethernet, not both at the same time.

                           Thanks in advance, HANYS


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Re: Ethernets on SCC2 and SCC3 on mpc8xx

[Wolfgang Denk]

Hello,

in message <3F3A3E2C.8040609@devcom.cz> you wrote:
>
> we want to use our custom board with MPC823e as
> easy firewall in our applications. We have two 10Mbit ethernet
> on board connected to SCC2 and SCC3 channels.
> Is it support in kernel
> for using both SCC channels configured as ethernet
> (eth0, eth1 devices) simultaneously ? I use 2.4.3 kernel

No, none of the public kernels supprts such  a  configurations.  Some
(ugly) patches (basicly duplicating the whole code) habe beeen posted
a  long,  long  time  ago.  You might find them in the archies. But a
rework of the driver shouldn't be oo difficult.


Best regards,

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
What was sliced bread the greatest thing since?

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RE: Ethernets on SCC2 and SCC3 on mpc8xx

[Iain Barker]

The FCC driver on 8260 supports up to 3 Ethernet ports. I don't think there
is any similar on the SCC used on 8xx (just one SCC can run Ethernet in the
standard driver, you choose which SCC) but if you are using 8xx with FEC you
can use one SCC and FEC to give two Ethernet ports on an 8xx.



-----Original Message-----
From: Jan Damborsky [mailto:jan.damborsky@devcom.cz]
Sent: Wednesday, 13 August, 2003 12:39
To: linuxppc-dev@lists.linuxppc.org
Subject: Ethernets on SCC2 and SCC3 on mpc8xx



Hello,

we want to use our custom board with MPC823e as
easy firewall in our applications. We have two 10Mbit ethernet
on board connected to SCC2 and SCC3 channels.
Is it support in kernel
for using both SCC channels configured as ethernet
(eth0, eth1 devices) simultaneously ? I use 2.4.3 kernel
and there is only possibility to use SCC2 or SCC3
as ethernet, not both at the same time.

                           Thanks in advance, HANYS


** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

Re: Ethernets on SCC2 and SCC3 on mpc8xx

[Jan Damborsky]

>The FCC driver on 8260 supports up to 3 Ethernet ports. I don't think there
>is any similar on the SCC used on 8xx (just one SCC can run Ethernet in the
>standard driver, you choose which SCC) but if you are using 8xx with FEC you
>can use one SCC and FEC to give two Ethernet ports on an 8xx.
>
But we use MPC823e which has not FEC (unfortunately). May be in future ?
So I have only SCCs for Etherenet. But driver modifying
should not be very difficult (as Wolfgang Denk wrote).

                                Thank you,
                                          HANYS


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Re: Ethernets on SCC2 and SCC3 on mpc8xx

[Dan Malek]

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Jan Damborsky wrote:

> So I will modify driver to work with both ethernets.

Attached is a patch for an old driver that I have given to many
people over the past couple of years that all promised they would
update the current source.  This never happened, so if anyone else
wants to try, have at it.

I don't like this patch due to the amount of code in the header
file that can only increase as more boards are added.  Please
remove this code and place it int some file, like enet_init.c or
something like that.

Thanks.


	-- Dan

[-- Attachment #2: enet_patch.gz --]
[-- Type: application/x-gzip, Size: 6750 bytes --]

Re: Ethernets on SCC2 and SCC3 on mpc8xx

[Jan Damborsky]

Dan Malek wrote:

> Attached is a patch for an old driver that I have given to many
> people over the past couple of years that all promised they would
> update the current source.  This never happened, so if anyone else
> wants to try, have at it.
>
> I don't like this patch due to the amount of code in the header
> file that can only increase as more boards are added.  Please
> remove this code and place it int some file, like enet_init.c or
> something like that.
>
Thank you. I will apply this patch as soon as I return from
holiday in September.
                                     Jan Damborsky


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Re: Ethernets on SCC2 and SCC3 on mpc8xx

[Brad Parker]

Wolfgang Denk wrote:
..
>>No, none of the public kernels supprts such  a  configurations.  Some
>>(ugly) patches (basicly duplicating the whole code) habe beeen posted
>>a  long,  long  time  ago.  You might find them in the archies. But a
>>rework of the driver shouldn't be oo difficult.

I did a reasonable version this for the 850/823 several years ago and
gave the patches to Dan Malek.  Bug him for them :-)

-brad


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Re: Ethernets on SCC2 and SCC3 on mpc8xx

[Joakim Tjernlund]

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Hi Jan

I have a version that supports multiple enet's in one driver.
It is a bit specific for our board and contains a lot more:
- run time settable MAC and MTU.
- optimized RX interrupt handling(up to 20% better throuput)
- improved handling of received faulty frames.

    I am attaching the driver. Good luck.

   Jocke

[-- Attachment #2: enet.c --]
[-- Type: application/octet-stream, Size: 34299 bytes --]

/*
 * Ethernet driver for Motorola MPC8xx.
 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
 *
 * I copied the basic skeleton from the lance driver, because I did not
 * know how to write the Linux driver, but I did know how the LANCE worked.
 *
 * This version of the driver is somewhat selectable for the different
 * processor/board combinations.  It works for the boards I know about
 * now, and should be easily modified to include others.  Some of the
 * configuration information is contained in "commproc.h" and the
 * remainder is here.
 *
 * Buffer descriptors are kept in the CPM dual port RAM, and the frame
 * buffers are in the host memory.
 *
 * Right now, I am very watseful with the buffers.  I allocate memory
 * pages and then divide them into 2K frame buffers.  This way I know I
 * have buffers large enough to hold one frame within one buffer descriptor.
 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
 * will be much more memory efficient and will easily handle lots of
 * small packets.
 *
 */
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>

#include <asm/8xx_immap.h>
#include <asm/pgtable.h>
#include <asm/mpc8xx.h>
#include <asm/bitops.h>
#include <asm/uaccess.h>

#include <asm/commproc.h>

/*
 *				Theory of Operation
 *
 * The MPC8xx CPM performs the Ethernet processing on SCC1.  It can use
 * an aribtrary number of buffers on byte boundaries, but must have at
 * least two receive buffers to prevent constant overrun conditions.
 *
 * The buffer descriptors are allocated from the CPM dual port memory
 * with the data buffers allocated from host memory, just like all other
 * serial communication protocols.  The host memory buffers are allocated
 * from the free page pool, and then divided into smaller receive and
 * transmit buffers.  The size of the buffers should be a power of two,
 * since that nicely divides the page.  This creates a ring buffer
 * structure similar to the LANCE and other controllers.
 *
 * Like the LANCE driver:
 * The driver runs as two independent, single-threaded flows of control.  One
 * is the send-packet routine, which enforces single-threaded use by the
 * cep->tx_busy flag.  The other thread is the interrupt handler, which is
 * single threaded by the hardware and other software.
 *
 * The send packet thread has partial control over the Tx ring and the
 * 'cep->tx_busy' flag.  It sets the tx_busy flag whenever it's queuing a Tx
 * packet. If the next queue slot is empty, it clears the tx_busy flag when
 * finished otherwise it sets the 'lp->tx_full' flag.
 *
 * The MBX has a control register external to the MPC8xx that has some
 * control of the Ethernet interface.  Information is in the manual for
 * your board.
 *
 * The RPX boards have an external control/status register.  Consult the
 * programming documents for details unique to your board.
 *
 * For the TQM8xx(L) modules, there is no control register interface.
 * All functions are directly controlled using I/O pins.  See commproc.h.
 */


/* The transmitter timeout
 */
#define TX_TIMEOUT	(1*HZ)

/* Define COPY_SMALL_FRAMES if you want to save buffer memory for small packets 
 * at a small performance hit */
#ifdef COPY_SMALL_FRAMES
  #define RX_COPYBREAK (256-16+1) /* dev_alloc_skb() adds 16 bytes for internal use */
#endif
/* The number of Tx and Rx buffers.  These are allocated from the page
 * pool.  The code may assume these are power of two, so it is best
 * to keep them that size.
 * We don't need to allocate pages for the transmitter.  We just use
 * the skbuffer directly.
 */

#ifdef CONFIG_ENET_BIG_BUFFERS
  #define RX_RING_SIZE		64
  #define TX_RING_SIZE		64	/* Must be power of two for this to work */
#else
  #define RX_RING_SIZE		16
  #define TX_RING_SIZE		16	/* Must be power of two for this to work */
#endif
#define TX_RING_MOD_MASK	(TX_RING_SIZE-1)

#define CPM_ENET_RX_FRSIZE	1552 /* must be a multiple of cache line */
#if CPM_ENET_RX_FRSIZE % L1_CACHE_LINE_SIZE != 0
    #error CPM_ENET_RX_FRSIZE must be a multiple of L1 cache size
#endif


/* The CPM stores dest/src/type, data, and checksum for receive packets.
 */
#define MAX_MTU 1514  /* this is data size */
#define MIN_MTU 46    /* this is data size */
#define SCC_MAX_MTU   (((CPM_ENET_RX_FRSIZE-ETH_HLEN-8)/4)*4) /* must be a multiple of 4 */

#define PKT_MAXBUF_SIZE   (MAX_MTU+ETH_HLEN+4) /* allow fullsized pppoe packets and VLAN */
#define PKT_MINBUF_SIZE   (MIN_MTU+ETH_HLEN+4)
#define PKT_MAXBLR_SIZE	  SCC_MAX_MTU


/* The CPM buffer descriptors track the ring buffers.  The rx_bd_base and
 * tx_bd_base always point to the base of the buffer descriptors.  The
 * cur_rx and cur_tx point to the currently available buffer.
 * The dirty_tx tracks the current buffer that is being sent by the
 * controller.  The cur_tx and dirty_tx are equal under both completely
 * empty and completely full conditions.  The empty/ready indicator in
 * the buffer descriptor determines the actual condition.
 */
struct scc_enet_private {
	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
	struct	sk_buff* tx_skbuff[TX_RING_SIZE];
	ushort	skb_cur;
	ushort	skb_dirty;

	/* CPM dual port RAM relative addresses.
	*/
	cbd_t	*rx_bd_base;		/* Address of Rx and Tx buffers. */
	cbd_t	*tx_bd_base;
	cbd_t	*cur_rx, *cur_tx;		/* The next free ring entry */
	cbd_t	*dirty_tx;	/* The ring entries to be free()ed. */
	scc_t	*sccp;

	/* Virtual addresses for the receive buffers because we can't
	 * do a __va() on them anymore.
	 */
	void    *rx_vaddr[RX_RING_SIZE];
	struct	net_device_stats stats;
	uint	tx_full;
        spinlock_t lock;
        char    scc_num;
        int     cpm_cr_ch;
};

int __init scc_enet_init_params(int scc_num, int cpmvec, int proff, int cpm_cr_ch);
int __init cpm_enet_init_scc_pins(int scc_num);
int __init cpm_enet_init_scc_clock(int scc_num);

static int scc_enet_open(struct net_device *dev);
static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
static int scc_enet_rx(struct net_device *dev);
static void scc_enet_interrupt(void *dev_id, struct pt_regs *regs);
static int scc_enet_close(struct net_device *dev);
static struct net_device_stats *scc_enet_get_stats(struct net_device *dev);
static void set_multicast_list(struct net_device *dev);
static void cpm_enet_enable_xmit(int);

/*
 * Called from net/core/dev.c: int dev_open(struct net_device *dev)
 *
 * If CONFIG_LUMENTISCP defined: it will be called twice, once for
 * 'eth0' and once for 'eth1'.
 *
 * If CONFIG_LUMENTISUP defined: it will be called just once.
 * I.e. for'eth0'.
 */

static int
scc_enet_open(struct net_device *dev)
{
	struct	scc_enet_private *cep = (struct scc_enet_private *)dev->priv;

	/* I should reset the ring buffers here, but I don't yet know
	 * a simple way to do that.
	 */
	netif_start_queue(dev);

	/* enable the transmit and receive processing.
	*/
	cep->sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	return 0;					/* Always succeed */
}

static int
scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
	volatile cbd_t	*bdp;
	volatile  scc_enet_t *ep = (scc_enet_t *)dev->base_addr;
	/* Fill in a Tx ring entry */
	bdp = cep->cur_tx;

	if (skb->len > (ep->sen_maxflr - 4)){
		printk("eth: TX frame is too long");
	}

	/* Clear all of the status flags.
	 */
	bdp->cbd_sc &= ~BD_ENET_TX_STATS;

	/* If the frame is short, tell CPM to pad it.
	if (skb->len <= ETH_ZLEN)
		bdp->cbd_sc |= BD_ENET_TX_PAD;
	else
		bdp->cbd_sc &= ~BD_ENET_TX_PAD;
	*/

	/* Set buffer length and buffer pointer.
	*/
	bdp->cbd_datlen = skb->len;
	bdp->cbd_bufaddr = __pa(skb->data);

	/* Save skb pointer.
	*/
	cep->tx_skbuff[cep->skb_cur] = skb;

	cep->stats.tx_bytes += skb->len;
	cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
	
	/* Push the data cache so the CPM does not get stale memory
	 * data.
	 */
	flush_dcache_range((unsigned long)(skb->data),
					(unsigned long)(skb->data + skb->len));

	spin_lock_irq(&cep->lock);

	/* Send it on its way.  Tell CPM its ready, interrupt when done,
	 * its the last BD of the frame, and to put the CRC on the end.
	 */
	bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_PAD);

	dev->trans_start = jiffies;

	/* If this was the last BD in the ring, start at the beginning again.
	*/
	if (bdp->cbd_sc & BD_ENET_TX_WRAP)
		bdp = cep->tx_bd_base;
	else
		bdp++;

	if (bdp->cbd_sc & BD_ENET_TX_READY) {
		netif_stop_queue(dev);
		cep->tx_full = 1;
	}

	cep->cur_tx = (cbd_t *)bdp;

	spin_unlock_irq(&cep->lock);

	return 0;
}

static void
scc_enet_timeout(struct net_device *dev)
{
	struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;

	printk("%s: transmit timed out.\n", dev->name);
	cep->stats.tx_errors++;
#ifndef final_version
	{
		int	i;
		cbd_t	*bdp;
		printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
		       cep->cur_tx, cep->tx_full ? " (full)" : "",
		       cep->cur_rx);
		bdp = cep->tx_bd_base;
		for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
			printk("%04x %04x %08x\n",
			       bdp->cbd_sc,
			       bdp->cbd_datlen,
			       bdp->cbd_bufaddr);
		bdp = cep->rx_bd_base;
		for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
			printk("%04x %04x %08x\n",
			       bdp->cbd_sc,
			       bdp->cbd_datlen,
			       bdp->cbd_bufaddr);
	}
#endif
	if (!cep->tx_full)
		netif_wake_queue(dev);
}

/* The interrupt handler.
 * This is called from the CPM handler, not the MPC core interrupt.
 */
static void
scc_enet_interrupt(void *dev_id,  struct pt_regs *regs)
{
	struct	net_device *dev = dev_id;
	volatile struct	scc_enet_private *cep;
	volatile cbd_t	*bdp;
	ushort	int_events;
	int	must_restart;

	cep = (struct scc_enet_private *)dev->priv;

	/* Get the interrupt events that caused us to be here.
	*/
	int_events = cep->sccp->scc_scce;
	cep->sccp->scc_scce = int_events;
	must_restart = 0;

	/* Handle receive event in its own function.
	*/
	if (int_events & SCCE_ENET_RXF)
		scc_enet_rx(dev_id);

	/* Check for a transmit error.  The manual is a little unclear
	 * about this, so the debug code until I get it figured out.  It
	 * appears that if TXE is set, then TXB is not set.  However,
	 * if carrier sense is lost during frame transmission, the TXE
	 * bit is set, "and continues the buffer transmission normally."
	 * I don't know if "normally" implies TXB is set when the buffer
	 * descriptor is closed.....trial and error :-).
	 */

	/* Transmit OK, or non-fatal error.  Update the buffer descriptors.
	*/
	if (int_events & (SCCE_ENET_TXE | SCCE_ENET_TXB)) {
	    spin_lock(&cep->lock);
	    bdp = cep->dirty_tx;
	    while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
		if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
		    break;
		if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN | BD_ENET_TX_CSL | BD_ENET_TX_RCMASK)) {
			if (bdp->cbd_sc & BD_ENET_TX_HB)	/* No heartbeat */
				cep->stats.tx_heartbeat_errors++;
			if (bdp->cbd_sc & BD_ENET_TX_LC)	/* Late collision */
				cep->stats.tx_window_errors++;
			if (bdp->cbd_sc & BD_ENET_TX_RL)	/* Retrans limit */
				cep->stats.tx_aborted_errors++;
			if (bdp->cbd_sc & BD_ENET_TX_UN)	/* Underrun */
				cep->stats.tx_fifo_errors++;
			if (bdp->cbd_sc & BD_ENET_TX_CSL)	/* Carrier lost */
				cep->stats.tx_carrier_errors++;
			
			/* Check retry counter, i.e. collision counter */
			if (bdp->cbd_sc & BD_ENET_TX_RCMASK){
				/* Note that counter cannot go higher than 15 */
				cep->stats.collisions+=(bdp->cbd_sc & BD_ENET_TX_RCMASK)>>2;
			}
			
			/* No heartbeat or Lost carrier are not really bad errors.
			 * The others require a restart transmit command.
			 */
			if (bdp->cbd_sc &
			    (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
				must_restart = 1;
				cep->stats.tx_errors++;
			}
		}

		cep->stats.tx_packets++;

		/* Free the sk buffer associated with this last transmit.
		*/
		dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
		cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;

		/* Update pointer to next buffer descriptor to be transmitted.
		*/
		if (bdp->cbd_sc & BD_ENET_TX_WRAP)
			bdp = cep->tx_bd_base;
		else
			bdp++;

		/* I don't know if we can be held off from processing these
		 * interrupts for more than one frame time.  I really hope
		 * not.  In such a case, we would now want to check the
		 * currently available BD (cur_tx) and determine if any
		 * buffers between the dirty_tx and cur_tx have also been
		 * sent.  We would want to process anything in between that
		 * does not have BD_ENET_TX_READY set.
		 */

		/* Since we have freed up a buffer, the ring is no longer
		 * full.
		 */
		if (cep->tx_full) {
			cep->tx_full = 0;
			if (netif_queue_stopped(dev))
				netif_wake_queue(dev);
		}

		cep->dirty_tx = (cbd_t *)bdp;
	    }

	    if (must_restart) {
		volatile cpm8xx_t *cp;

		/* Some transmit errors cause the transmitter to shut
		 * down.  We now issue a restart transmit.  Since the
		 * errors close the BD and update the pointers, the restart
		 * _should_ pick up without having to reset any of our
		 * pointers either.
		 */
		cp = cpmp;
		cp->cp_cpcr =
                    mk_cr_cmd(cep->cpm_cr_ch, CPM_CR_RESTART_TX) | CPM_CR_FLG;
		while (cp->cp_cpcr & CPM_CR_FLG);
	    }
	    spin_unlock(&cep->lock);
	}

	/* Check for receive busy, i.e. packets coming but no place to
	 * put them.  This "can't happen" because the receive interrupt
	 * is tossing previous frames.
	 */
	if (int_events & SCCE_ENET_BSY) {
		cep->stats.rx_dropped++;
		printk("CPM ENET ethernet: BSY can't happen.\n");
	}

	return;
}

/* During a receive, the cur_rx points to the current incoming buffer.
 * When we update through the ring, if the next incoming buffer has
 * not been given to the system, we just set the empty indicator,
 * effectively tossing the packet.
 */
static int
scc_enet_rx(struct net_device *dev)
{
	struct	scc_enet_private *cep;
	volatile cbd_t	*bdp;
	struct	sk_buff *skb, *skb_tmp;
	ushort	pkt_len;

	cep = (struct scc_enet_private *)dev->priv;

	/* First, grab all of the stats for the incoming packet.
	 * These get messed up if we get called due to a busy condition.
	 */
	bdp = cep->cur_rx;

	for (;;) {
		if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
			break;
#define RX_BD_ERRORS (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_CL)
		if(bdp->cbd_sc & RX_BD_ERRORS){ /* Receive errors ? */
			cep->stats.rx_errors++;
			if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) /* Frame too long or too short. */
				cep->stats.rx_length_errors++;
			if (bdp->cbd_sc & BD_ENET_RX_NO)	/* Frame alignment */
				cep->stats.rx_frame_errors++;
			if (bdp->cbd_sc & BD_ENET_RX_CR)	/* CRC Error */
				cep->stats.rx_crc_errors++;
			if (bdp->cbd_sc & BD_ENET_RX_OV)	/* FIFO overrun */
				cep->stats.rx_fifo_errors++;
			if (bdp->cbd_sc & BD_ENET_RX_CL)        /* Late collision */
				cep->stats.collisions++;
		} else {
			
			/* Process the incoming frame.
			 */
			cep->stats.rx_packets++;
			pkt_len = bdp->cbd_datlen;
			cep->stats.rx_bytes += pkt_len;
			pkt_len -= 4; /* The packet length includes FCS, but we don't want to
				       * include that when passing upstream as it messes up
				       * bridging applications. */
#ifdef COPY_SMALL_FRAMES 
			/* Allocate the next buffer now so we are sure to have one when needed
			 * This does 16 byte alignment, exactly what we need(L1_CACHE aligned). */
			if(pkt_len < RX_COPYBREAK){
				skb_tmp = __dev_alloc_skb(pkt_len + 2, GFP_ATOMIC | GFP_DMA);
				skb_reserve(skb_tmp, 2); /* make the IP header L1 cache aligned */
			} else
#endif
				skb_tmp = __dev_alloc_skb(CPM_ENET_RX_FRSIZE, GFP_ATOMIC | GFP_DMA);
			
			if (skb_tmp == NULL) {
				printk("%s: Memory squeeze, dropping packet.\n", dev->name);
				cep->stats.rx_dropped++;

			} else {
				skb = cep->rx_vaddr[bdp - cep->rx_bd_base];
#ifdef COPY_SMALL_FRAMES 
				if(pkt_len < RX_COPYBREAK) {
					typeof(skb) skb_swap = skb;
					memcpy(skb_put(skb_tmp, pkt_len), skb->data, pkt_len);
					/* swap the skb and skb_tmp */
					skb = skb_tmp;
					skb_tmp = skb_swap;
				} 
				else 
#endif
				{
					skb_put(skb, pkt_len);  /* Make room */
					bdp->cbd_bufaddr = __pa(skb_tmp->data);
					cep->rx_vaddr[bdp - cep->rx_bd_base] = skb_tmp;
				}
				invalidate_dcache_range((unsigned long) skb_tmp->data,
							(unsigned long) skb_tmp->data + CPM_ENET_RX_FRSIZE);
				skb->dev = dev;
				skb->protocol=eth_type_trans(skb, dev);
				netif_rx(skb);
			}
		}
		
		/* Clear the status flags for this buffer.
		 */
		bdp->cbd_sc &= ~BD_ENET_RX_STATS;
		
		/* Mark the buffer empty.
		 */
		bdp->cbd_sc |= BD_ENET_RX_EMPTY;
		
		/* Update BD pointer to next entry.
		 */
		if (bdp->cbd_sc & BD_ENET_RX_WRAP)
			bdp = cep->rx_bd_base;
		else
			bdp++;
		
	}
	cep->cur_rx = (cbd_t *)bdp;

	return 0;
}

static int
scc_enet_close(struct net_device *dev)
{
	struct	scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
	/* Don't know what to do yet.
	*/
	cep->sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	netif_stop_queue(dev);

	return 0;
}

static struct net_device_stats *scc_enet_get_stats(struct net_device *dev)
{
	struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;

	return &cep->stats;
}

static int change_mtu(struct net_device *dev, int new_mtu)
{
	volatile scc_enet_t *ep;

	if ((new_mtu < MIN_MTU ) || (new_mtu >  MAX_MTU))
	       return -EINVAL;
	ep = (scc_enet_t *)dev->base_addr;
	
	ep->sen_maxflr = new_mtu + ETH_HLEN + 4;   /* maximum frame length register */
	dev->mtu = new_mtu;
	printk("ENET: change_mtu: %d\n",new_mtu);
	return 0;
}

static int set_mac_address(struct net_device *dev, void *addr)
{
	volatile scc_enet_t *ep;
	unsigned char	    *eap;
	struct sockaddr     *mac = addr;
	int	i;

	if(netif_running(dev))
	       return -EBUSY;
	
	/* Get pointer to SCC area in parameter RAM. */
	ep = (scc_enet_t *)dev->base_addr;
	eap = (unsigned char *)&(ep->sen_paddrh);
	/* cli();  */
	for (i=5; i>=0; i--)
		*eap++ = dev->dev_addr[i] = mac->sa_data[i];
	/* sti(); */
	return 0;
}

/* Set or clear the multicast filter for this adaptor.
 * Skeleton taken from sunlance driver.
 * The CPM Ethernet implementation allows Multicast as well as individual
 * MAC address filtering.  Some of the drivers check to make sure it is
 * a group multicast address, and discard those that are not.  I guess I
 * will do the same for now, but just remove the test if you want
 * individual filtering as well (do the upper net layers want or support
 * this kind of feature?).
 */

static void set_multicast_list(struct net_device *dev)
{
	struct	scc_enet_private *cep;
	struct	dev_mc_list *dmi;
	u_char	*mcptr, *tdptr;
	volatile scc_enet_t *ep;
	int	i, j;
	cep = (struct scc_enet_private *)dev->priv;

	/* Get pointer to SCC area in parameter RAM.
	*/
	ep = (scc_enet_t *)dev->base_addr;

	if (dev->flags&IFF_PROMISC) {
		cep->sccp->scc_pmsr |= SCC_PMSR_PRO;
	} else {

		cep->sccp->scc_pmsr &= ~SCC_PMSR_PRO;

		if (dev->flags & IFF_ALLMULTI) {
			/* Catch all multicast addresses, so set the
			 * filter to all 1's.
			 */
			ep->sen_gaddr1 = 0xffff;
			ep->sen_gaddr2 = 0xffff;
			ep->sen_gaddr3 = 0xffff;
			ep->sen_gaddr4 = 0xffff;
		}
		else {
			/* Clear filter and add the addresses in the list.
			*/
			ep->sen_gaddr1 = 0;
			ep->sen_gaddr2 = 0;
			ep->sen_gaddr3 = 0;
			ep->sen_gaddr4 = 0;

			dmi = dev->mc_list;

			for (i=0; i<dev->mc_count; i++, dmi = dmi->next) {
				
				/* Only support group multicast for now.
				*/
				if (!(dmi->dmi_addr[0] & 1))
					continue;

				/* The address in dmi_addr is LSB first,
				 * and taddr is MSB first.  We have to
				 * copy bytes MSB first from dmi_addr.
				 */
				mcptr = (u_char *)dmi->dmi_addr + 5;
				tdptr = (u_char *)&ep->sen_taddrh;
				for (j=0; j<6; j++)
					*tdptr++ = *mcptr--;

				/* Ask CPM to run CRC and set bit in
				 * filter mask.
				 */
                                cpmp->cp_cpcr = mk_cr_cmd(cep->cpm_cr_ch, CPM_CR_SET_GADDR) | CPM_CR_FLG;
				/* this delay is necessary here -- Cort */
				udelay(10);
				while (cpmp->cp_cpcr & CPM_CR_FLG);

			}
		}
	}
}

int __init scc_enet_init(void)
{
	bd_t *bd = (bd_t *)__res;
	/*
	 * Always initialize eth0 on SCC1.
	 */
	scc_enet_init_params(0, CPMVEC_SCC1, PROFF_SCC1, CPM_CR_CH_SCC1);
	
	if(bd->board_type ==  CU_BOARDTYPE || bd->board_type ==  CU2_BOARDTYPE){
		/*
		 * On a CP board initialize eth1 on SCC2.
		 */
		scc_enet_init_params(1, CPMVEC_SCC2, PROFF_SCC2, CPM_CR_CH_SCC2);
		if(bd->board_type ==  CU2_BOARDTYPE){
			scc_enet_init_params(3, CPMVEC_SCC4, PROFF_SCC4, CPM_CR_CH_SCC4);
		}
	}
	return 0;
}


/* Initialize the CPM Ethernet on SCC.  If EPPC-Bug loaded us, or performed
 * some other network I/O, a whole bunch of this has already been set up.
 * It is no big deal if we do it again, we just have to disable the
 * transmit and receive to make sure we don't catch the CPM with some
 * inconsistent control information.
 */
int __init scc_enet_init_params(int scc_num, int cpmvec, int proff, int cpm_cr_ch)
{
	struct net_device *dev;
	struct scc_enet_private *cep;
	int i, j, k;
	unsigned char	*eap;
	bd_t		*bd;
	volatile	cbd_t		*bdp;
	volatile	cpm8xx_t	*cp;
	volatile	scc_t		*sccp;
	volatile	scc_enet_t	*ep;
	volatile	immap_t		*immap;

	cp = cpmp;	/* Get pointer to Communication Processor */

	immap = (immap_t *)(mfspr(IMMR) & 0xFFFF0000);	/* and to internal registers */

	bd = (bd_t *)__res;

	/* Allocate some private information.
	*/
	cep = (struct scc_enet_private *)kmalloc(sizeof(*cep), GFP_KERNEL);
	if (cep == NULL)
		return -ENOMEM;

	__clear_user(cep,sizeof(*cep));
	spin_lock_init(&cep->lock);

	/* Create an Ethernet device instance.
	*/
	dev = init_etherdev(0, 0);

	/* Get pointer to SCC area in parameter RAM.
	*/
        ep = (scc_enet_t *)(&cp->cp_dparam[proff]);

	/* And another to the SCC register area.
	*/
        sccp = (volatile scc_t *)(&cp->cp_scc[scc_num]);
	cep->sccp = (scc_t *)sccp;		/* Keep the pointer handy */
        cep->scc_num = scc_num;
        cep->cpm_cr_ch = cpm_cr_ch;

	/* Disable receive and transmit in case EPPC-Bug started it.
	*/
	sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	/* Init physical pins
	 */
	cpm_enet_init_scc_pins(scc_num);

	/* Configure Serial Interface clock routing.
	 */
	cpm_enet_init_scc_clock(scc_num);


	/* Manual says set SDDR, but I can't find anything with that
	 * name.  I think it is a misprint, and should be SDCR.  This
	 * has already been set by the communication processor initialization.
	 */

	/* Allocate space for the buffer descriptors in the DP ram.
	 * These are relative offsets in the DP ram address space.
	 * Initialize base addresses for the buffer descriptors.
	 */
	i = m8xx_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE);
	ep->sen_genscc.scc_rbase = i;
	cep->rx_bd_base = (cbd_t *)&cp->cp_dpmem[i];

	i = m8xx_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE);
	ep->sen_genscc.scc_tbase = i;
	cep->tx_bd_base = (cbd_t *)&cp->cp_dpmem[i];

	cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
	cep->cur_rx = cep->rx_bd_base;

	/* Issue init Rx BD command for SCC.
	 * Manual says to perform an Init Rx parameters here.  We have
	 * to perform both Rx and Tx because the SCC may have been
	 * already running.
	 * In addition, we have to do it later because we don't yet have
	 * all of the BD control/status set properly.
	 */

	/* Initialize function code registers for big-endian.
	*/
	ep->sen_genscc.scc_rfcr = SCC_EB;
	ep->sen_genscc.scc_tfcr = SCC_EB;

	/* Set maximum bytes per receive buffer.
	 * This appears to be an Ethernet frame size, not the buffer
	 * fragment size.  It must be a multiple of four.
	 */
	ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE;

	/* Set CRC preset and mask.
	*/
	ep->sen_cpres = 0xffffffff;
	ep->sen_cmask = 0xdebb20e3;

	ep->sen_crcec = 0;	/* CRC Error counter */
	ep->sen_alec = 0;	/* alignment error counter */
	ep->sen_disfc = 0;	/* discard frame counter */

	ep->sen_pads = 0x8888;	/* Tx short frame pad character */
	ep->sen_retlim = 15;	/* Retry limit threshold */

	ep->sen_maxflr = PKT_MAXBUF_SIZE;   /* maximum frame length register */
	ep->sen_minflr = PKT_MINBUF_SIZE;  /* minimum frame length register */

	ep->sen_maxd1 = PKT_MAXBLR_SIZE;	/* maximum DMA1 length */
	ep->sen_maxd2 = PKT_MAXBLR_SIZE;	/* maximum DMA2 length */

	/* Clear hash tables.
	*/
	ep->sen_gaddr1 = 0;
	ep->sen_gaddr2 = 0;
	ep->sen_gaddr3 = 0;
	ep->sen_gaddr4 = 0;
	ep->sen_iaddr1 = 0;
	ep->sen_iaddr2 = 0;
	ep->sen_iaddr3 = 0;
	ep->sen_iaddr4 = 0;
	/* Set Ethernet station address.
	 *
	 * If we performed a MBX diskless boot, the Ethernet controller
	 * has been initialized and we copy the address out into our
	 * own structure.
	 *
	 * All other types of boards supply the address in the board
	 * information structure, so we copy that into the controller.
	 */
	eap = (unsigned char *)&(ep->sen_paddrh);
	for (i=5; i>=0; i--)
		*eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];

	ep->sen_pper = 0;	/* 'cause the book says so */
	ep->sen_taddrl = 0;	/* temp address (LSB) */
	ep->sen_taddrm = 0;
	ep->sen_taddrh = 0;	/* temp address (MSB) */

	/* Now allocate the host memory pages and initialize the
	 * buffer descriptors.
	 */
	bdp = cep->tx_bd_base;
	for (i=0; i<TX_RING_SIZE; i++) {

		/* Initialize the BD for every fragment in the page.
		*/
		bdp->cbd_sc = 0;
		bdp->cbd_bufaddr = 0;
		bdp++;
	}

	/* Set the last buffer to wrap.
	*/
	bdp--;
	bdp->cbd_sc |= BD_SC_WRAP;

	bdp = cep->rx_bd_base;
	k = 0;
	/* Initialize the BDs. */
	for (j=0; j < RX_RING_SIZE; j++) {
		struct	sk_buff * skb = __dev_alloc_skb(CPM_ENET_RX_FRSIZE, GFP_ATOMIC|GFP_DMA);

		invalidate_dcache_range((unsigned long) skb->data,
					(unsigned long) skb->data + CPM_ENET_RX_FRSIZE);
		bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
		bdp->cbd_bufaddr = __pa(skb->data);
		cep->rx_vaddr[k++] = skb;
		bdp++;
	}
	/* Set the last buffer to wrap.
	*/
	bdp--;
	bdp->cbd_sc |= BD_SC_WRAP;

	/* Let's re-initialize the channel now.  We have to do it later
	 * than the manual describes because we have just now finished
	 * the BD initialization.
	 */
        cp->cp_cpcr = mk_cr_cmd(cep->cpm_cr_ch, CPM_CR_INIT_TRX) | CPM_CR_FLG;
	while (cp->cp_cpcr & CPM_CR_FLG);

	cep->skb_cur = cep->skb_dirty = 0;

	sccp->scc_scce = 0xffff;	/* Clear any pending events */

	/* Enable interrupts for transmit error, complete frame
	 * received, and any transmit buffer we have also set the
	 * interrupt flag.
	 */
	sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);

	/* Install our interrupt handler.
	*/
        cpm_install_handler(cpmvec, scc_enet_interrupt, dev);

	/* Set GSMR_H to enable all normal operating modes.
	 * Set GSMR_L to enable Ethernet to MC68160.
	 */
	sccp->scc_gsmrh = 0;
	sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET);

	/* Set sync/delimiters.
	*/
	sccp->scc_dsr = 0xd555;

	/* Set processing mode.  Use Ethernet CRC, catch broadcast, and
	 * start frame search 22 bit times after RENA.
	 */
	sccp->scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22);
#ifdef CONFIG_SCC_ENET_FULL_DUPLEX 
	sccp->scc_pmsr |= SCC_PMSR_LPB | SCC_PMSR_FDE;
	printk("Enet %d: Full duplex enabled\n", scc_num);
#endif
	/* It is now OK to enable the Ethernet transmitter.
	 * Unfortunately, there are board implementation differences here.
	 */
        cpm_enet_enable_xmit(scc_num);


#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
	/* And while we are here, set the configuration to enable ethernet.
	*/
	*((volatile uint *)RPX_CSR_ADDR) &= ~BCSR0_ETHLPBK;
	*((volatile uint *)RPX_CSR_ADDR) |=
			(BCSR0_ETHEN | BCSR0_COLTESTDIS | BCSR0_FULLDPLXDIS);

#endif


	dev->base_addr = (unsigned long)ep;
	dev->priv = cep;
#if 0
	dev->name = "CPM_ENET";
#endif

	/* The CPM Ethernet specific entries in the device structure. */
	dev->open = scc_enet_open;
	dev->hard_start_xmit = scc_enet_start_xmit;
	dev->tx_timeout = scc_enet_timeout;
	dev->watchdog_timeo = TX_TIMEOUT;
	dev->stop = scc_enet_close;
	dev->get_stats = scc_enet_get_stats;
	dev->set_multicast_list = set_multicast_list;
	dev->set_mac_address = set_mac_address;
	dev->change_mtu = change_mtu;

	printk("%s: CPM ENET Version 0.3, ", dev->name);
	for (i=0; i<5; i++)
		printk("%02x:", dev->dev_addr[i]);
	printk("%02x\n", dev->dev_addr[5]);

	return 0;
}

/* Cookbook style from the MPC860 manual.....
 * Not all of this is necessary if EPPC-Bug has initialized
 * the network.
 * So far we are lucky, all board configurations use the same
 * pins, or at least the same I/O Port for these functions.....
 * It can't last though......
 */

int __init cpm_enet_init_scc_pins(int scc_num)
{
    volatile immap_t *immap = (immap_t *)IMAP_ADDR;

    switch (scc_num) {
    case 0: /* SCC1 */
        /* Configure port A pins for Txd and Rxd.
         */
        immap->im_ioport.iop_papar |= (PA1_ENET_RXD | PA1_ENET_TXD);
        immap->im_ioport.iop_padir &= ~(PA1_ENET_RXD | PA1_ENET_TXD);
        immap->im_ioport.iop_paodr &= ~PA1_ENET_TXD;

        /* Configure port C pins to enable CLSN and RENA.
         */
        immap->im_ioport.iop_pcpar &= ~(PC1_ENET_CLSN | PC1_ENET_RENA);
        immap->im_ioport.iop_pcdir &= ~(PC1_ENET_CLSN | PC1_ENET_RENA);
        immap->im_ioport.iop_pcso |= (PC1_ENET_CLSN | PC1_ENET_RENA);

        /* Configure port A for TCLK and RCLK.
         */
        immap->im_ioport.iop_papar |= (PA1_ENET_TCLK | PA1_ENET_RCLK);
        immap->im_ioport.iop_padir &= ~(PA1_ENET_TCLK | PA1_ENET_RCLK);
        break;

    case 1: /* SCC2 */
        /* Configure port A pins for Txd and Rxd.
         */
        immap->im_ioport.iop_papar |= (PA2_ENET_RXD | PA2_ENET_TXD);
        immap->im_ioport.iop_padir &= ~(PA2_ENET_RXD | PA2_ENET_TXD);
        immap->im_ioport.iop_paodr &= ~PA2_ENET_TXD;

        /* Configure port C pins to enable CLSN and RENA.
         */
        immap->im_ioport.iop_pcpar &= ~(PC2_ENET_CLSN | PC2_ENET_RENA);
        immap->im_ioport.iop_pcdir &= ~(PC2_ENET_CLSN | PC2_ENET_RENA);
        immap->im_ioport.iop_pcso |= (PC2_ENET_CLSN | PC2_ENET_RENA);

        /* Configure port A for TCLK and RCLK.
         * eth1 on CP board: TCLK: CLK3    0x0400
         *                   RCLK: CLK4    0x0800
         */
        immap->im_ioport.iop_papar |= (PA2_ENET_TCLK | PA2_ENET_RCLK);
        immap->im_ioport.iop_padir &= ~(PA2_ENET_TCLK | PA2_ENET_RCLK);
        break;

    case 3: /* SCC4 */
        /* Configure port D pins for Txd and Rxd.
         */
        immap->im_ioport.iop_pdpar |= (PD4_ENET_RXD | PD4_ENET_TXD);
	/* Make sure PDDIR is zero otherwise RXD and TXD wont work on PD pins! */
        immap->im_ioport.iop_pddir &= ~(PD4_ENET_RXD | PD4_ENET_TXD);

        /* Configure port C pins to enable CLSN and RENA.
         */
        immap->im_ioport.iop_pcpar &= ~(PC4_ENET_CLSN | PC4_ENET_RENA);
        immap->im_ioport.iop_pcdir &= ~(PC4_ENET_CLSN | PC4_ENET_RENA);
        immap->im_ioport.iop_pcso |= (PC4_ENET_CLSN | PC4_ENET_RENA);

        /* Configure port A for TCLK and RCLK.
         * eth2 on CP board: TCLK: CLK7    0x8000
         *                   RCLK: CLK8    0x4000
         */
        immap->im_ioport.iop_papar |= (PA4_ENET_TCLK | PA4_ENET_RCLK);
        immap->im_ioport.iop_padir &= ~(PA4_ENET_TCLK | PA4_ENET_RCLK);
        break;
    default:
        break;
    }

    return 0;
}

int __init cpm_enet_init_scc_clock(int scc_num)
{
    volatile cpm8xx_t *cp = cpmp;

    /* First, clear all SCC bits to zero, then set the ones we want.
     */
    switch (scc_num) {
    case 0:
        cp->cp_sicr &= ~SICR_ENET_MASK_1;
        /*
         * 'First ethernet, eth0:
         * TCLK: CLK1    RCLK: CLK2
         */
        cp->cp_sicr |= SICR_ENET_CLKRT_1;  /* 0x0000002C */
        break;
    case 1:
        /*
         * 'Second ethernet, eth1:
         * TCLK: CLK3    RCLK: CLK4
         */
        cp->cp_sicr &= ~SICR_ENET_MASK_2; /* 0x0000ff00 */
        cp->cp_sicr |= SICR_ENET_CLKRT_2; /* 0x00003E00 */
        break;
    case 3:
        /*
         * eth2:
         * TCLK: CLK7    RCLK: CLK8
         */
        cp->cp_sicr &= ~SICR_ENET_MASK_4; /* 0xff000000 */
        cp->cp_sicr |= SICR_ENET_CLKRT_4; /* 0x3E000000 */
        break;
    default:
        break;
    }
    return 0;
}

static void cpm_enet_enable_xmit(int scc_num)
{
    volatile immap_t *immap = (immap_t *)IMAP_ADDR;
    volatile cpm8xx_t *cp = cpmp;

    switch (scc_num) {
    case 0: /* SCC1 */
	cp->cp_pbpar |= PB1_ENET_TENA;
	cp->cp_pbdir |= PB1_ENET_TENA;
        break;
    case 1: /* SCC2 */
	cp->cp_pbpar |= PB2_ENET_TENA;
	cp->cp_pbdir |= PB2_ENET_TENA;
        break;
    case 3: /* SCC4 */
        immap->im_ioport.iop_pdpar |= PD4_ENET_TENA;
	/* Make sure PDDIR is zero otherwise TENA wont work on PD pins! */
        immap->im_ioport.iop_pddir &= ~PD4_ENET_TENA;
        break;
    default:
        break;
    }
}