From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp1.us4.outblaze.com (smtp1.us4.outblaze.com [205.158.62.78]) by ozlabs.org (Postfix) with SMTP id 14A6C67AC7 for ; Fri, 24 Mar 2006 06:55:43 +1100 (EST) Message-ID: <00c701c64eb3$c23b0c40$6401a8c0@CHUCK2> From: "Mark Chambers" To: "David Hawkins" References: <204E7000-3E88-4497-86C0-5AF786D72F75@kernel.crashing.org><4422D6E3.1010407@ovro.caltech.edu> <00be01c64ea1$4c6e0e20$6401a8c0@CHUCK2> <4422E0CB.8080701@ovro.caltech.edu> Subject: Re: Memory mapping PCI memory region to user space Date: Thu, 23 Mar 2006 14:55:35 -0500 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=response Cc: "Linuxppc-Embedded \(\(E-Mail\)\)" List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , > >> >> PCI is actually endian-agnostic, so we're really 'fixing' the >> Freescale PCI implementation with endian swapping. >> > > Hi Mark, > > Its not agnostic, its little-endian. > Ok, I should be a little more specific. Yes, I/O space is little endian, and any configuration registers and such are little endian. But memory space is strictly 32 bit as far as PCI is concerned. (forgetting 64 bit PCI for the moment) The two lower bits of address are not used, and there is no required correlation of byte enables to those missing address bits. So, the point is, Freescale swaps bytes between its internal bus and PCI. Other processors (like TI DSPs) do not. I don't know that one method is necessarily right, but the fact that we have this discussion periodically suggests that Freescale's method is not the best. This might be an academic point, but I think it does help to see the distinction. To talk to a device over PCI you must know how both ends map their internal buss(es) to PCI, and it's not directly a big/little endian issue. Mark