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Thu, 8 Apr 2021 02:38:23 +0000 (GMT) Received: from Madhavan.PrimaryTP (unknown [9.85.181.214]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 8 Apr 2021 02:38:23 +0000 (GMT) Subject: Re: [PATCH v3 1/2] powerpc/perf: Infrastructure to support checking of attr.config* To: Michael Ellerman References: <20210325115326.143151-1-maddy@linux.ibm.com> <87sg42e34x.fsf@mpe.ellerman.id.au> From: Madhavan Srinivasan Message-ID: <01370595-7135-1cb1-5998-76e169617b1b@linux.ibm.com> Date: Thu, 8 Apr 2021 08:08:22 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <87sg42e34x.fsf@mpe.ellerman.id.au> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: lF0FrRBW9vTDel5kiG00fqblrg-fmxJt X-Proofpoint-ORIG-GUID: lF0FrRBW9vTDel5kiG00fqblrg-fmxJt X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-07_11:2021-04-07, 2021-04-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 mlxscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104080014 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 4/7/21 5:08 PM, Michael Ellerman wrote: > Madhavan Srinivasan writes: >> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c >> index 6817331e22ff..c6eeb4fdc5fd 100644 >> --- a/arch/powerpc/perf/core-book3s.c >> +++ b/arch/powerpc/perf/core-book3s.c >> @@ -1958,6 +1958,20 @@ static int power_pmu_event_init(struct perf_event *event) >> >> if (ppmu->blacklist_ev && is_event_blacklisted(ev)) >> return -EINVAL; >> + /* >> + * PMU config registers have fields that are >> + * reserved and specific value to bit field as reserved. >> + * For ex., MMCRA[61:62] is Randome Sampling Mode (SM) >> + * and value of 0b11 to this field is reserved. >> + * >> + * This check is needed only for raw event type, >> + * since tools like fuzzer use raw event type to >> + * provide randomized event code values for test. >> + * >> + */ >> + if (ppmu->check_attr_config && >> + ppmu->check_attr_config(event)) >> + return -EINVAL; >> break; > It's not obvious from the diff, but you're only doing the check for RAW > events. > > But I think that's wrong, we should always check, even if the event code > comes from the kernel we should still apply the same checks. Otherwise > we might inadvertently use an invalid event code for a HARDWARE or CACHE Reason for not including HARDWARE and CACHE events are thats, they are straight forward, meaning they dont use sampling or thresholding features. Currently, checks are mostly in that spaces to check for any invalid values. We could include the check for all types the events. I will respin the patch with that change Thanks for review Maddy > event. > > cheers