From: "kerler" <kerler@mailandnews.com>
To: "David Edelsohn" <dje@watson.ibm.com>
Cc: <linuxppc-dev@lists.linuxppc.org>
Subject: Re: dynamic modification exception handler
Date: Tue, 27 Feb 2001 10:08:52 +0800 [thread overview]
Message-ID: <01ef01c0a062$a80939f0$5ef1d092@chn.agilent.com> (raw)
In-Reply-To: 200102261835.NAA26566@mal-ach.watson.ibm.com
Hi,
I add sync between icbi and isync. But the executed codes are still the
stale codes. Is cache coherence related with address translation of MMU?
-----------method 2----------
static inline void store_inst(void *p)
{
asm volatile ("dcbst 0,%0; sync; icbi 0,%0; sync; isync" : : "r" (p));
}
void mdb_flush_cache (const unsigned int start, const unsigned int len)
{
unsigned int i;
for ( i = start ; i <= len + start ; i ++ )
{
store_inst((void*)start);
}
}
------------end of method 2------
----- Original Message -----
From: David Edelsohn <dje@watson.ibm.com>
To: kerler <kerler@mailandnews.com>
Cc: <linuxppc-dev@lists.linuxppc.org>
Sent: Tuesday, February 27, 2001 2:35 AM
Subject: Re: dynamic modification exception handler
>
> The suggested sequence for 604 and 604-derived processors is:
>
> dcbst (or dcbf) ;# flush data block to memory
> sync ;# ensure flush made it to memory
> icbi ;# invalidate block from icache
> sync ;# wait for icbi to be globally performed
> isync ;# refetch instructions
>
> The dcbst must be performed before the icbi, because otherwise the
> processor instruction prefetch mechanism could refetch the (stale) block
> from memory before the dcbst/dcbf has actually been written back to
> memory. The sync between them is required for the same reason, because
> icbi could be performed locally before the dcbst has sent the block to
> memory.
>
> The dcbst/sync/icbi sequence can be batched up to amortize the
> cost of the sync operations, but it should be written so all the dcbst's
> are performed, then a sync, then all the icbi's:
>
> mr r5, r3
> mtctr blocks
> $1:
> dcbst r0, r5
> addi r5, r5, 32
> bdnz $1
> sync
> mr r5, r3
> mtctr blocks
> $2:
> icbi r0, r5
> addi r5, r5, 32
> bdnz $2
>
> sync
> isync
>
>
> David
>
>
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2001-02-27 2:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-02-19 9:04 why there is NOT support for FADS board ? Rolf Liu
2001-02-19 17:57 ` Wolfgang Denk
2001-02-19 18:10 ` Dan Malek
2001-02-26 11:06 ` dynamic modification exception handler kerler
2001-02-26 18:35 ` David Edelsohn
2001-02-27 2:08 ` kerler [this message]
2001-03-01 3:49 ` kerler
2001-03-01 4:11 ` David Edelsohn
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='01ef01c0a062$a80939f0$5ef1d092@chn.agilent.com' \
--to=kerler@mailandnews.com \
--cc=dje@watson.ibm.com \
--cc=linuxppc-dev@lists.linuxppc.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).