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charset=utf-8 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3864.300.41.1.7\)) Subject: Re: [PATCH] powerpc/perf: Update check for PERF_SAMPLE_DATA_SRC marked events From: Athira Rajeev In-Reply-To: <20260421150628.96500-1-shivani@linux.ibm.com> Date: Thu, 23 Apr 2026 23:20:42 +0530 Cc: maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, hbathini@linux.vnet.ibm.com, Tejas.Manhas1@ibm.com Content-Transfer-Encoding: quoted-printable Message-Id: <02211194-CC8D-496B-A701-41453A01FB48@linux.ibm.com> References: <20260421150628.96500-1-shivani@linux.ibm.com> To: Shivani Nittor X-Mailer: Apple Mail (2.3864.300.41.1.7) X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIzMDE3MyBTYWx0ZWRfXyfa0rWF9vPOF WN0HsS7qvWXWK9rfuwnL7lAMaOr4kohqArC3hH3YDJ/fjfCuT+20776do7L5A+LU8HJJZjms5bu 4PA97a7830lERabyL6DmlNRUO/wDxgXNUPSpG1JEmNL1ZUL/mNcHiScb6+UaUaEZYGg0hZgP3Gi bhvGEo9poxZfaQF9rW0n1d0iQjM2EBm/jepgkNRs838fWcun1tb7/ufqJFeHdNG84DQ8k1TpUEF bNjPBu9SqJSbybkj9L0W5d7cIP7j48hUJScc/Mb3xVWXGrkCFo1FxpJwvkigtPiH93FWRu1ThGi BDiQQGBIzCjp7zA/fQzdonSNuufoW2n2Tijrh/ibhDVNV1z4Yj0I1PD/gRDgZHJWu45sgcjnRxs xEMZY/8jGOV050jXsgVNuo9eWPWTmGJcxwSKZjmiGN/mD0tezDzaiD/3EkHA9bPZsSKgLLzNj8V +zfnuGadiwXzk32Oahw== X-Proofpoint-ORIG-GUID: tqLDWfuDlpvydnFx8mkAdyB2uZPZwDK- X-Proofpoint-GUID: tqLDWfuDlpvydnFx8mkAdyB2uZPZwDK- X-Authority-Analysis: v=2.4 cv=BYfoFLt2 c=1 sm=1 tr=0 ts=69ea5c04 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=b0JcJouLdBaXTkySTX0A:9 a=lqcHg5cX4UMA:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230173 > On 21 Apr 2026, at 8:36=E2=80=AFPM, Shivani Nittor = wrote: >=20 > The core-book3s PMU sampling code validates the SIER TYPE field > when PERF_SAMPLE_DATA_SRC is requested. The SIER TYPE field > indicates the instruction type and is only valid for > random sampling (marked events). To handle cases observed where > SIER TYPE could be zero even for marked events,validation was > added to drop such samples and increment event->lost_samples. >=20 > However, this validation was applied to all samples, > including continuous sampling. In continuous sampling mode, > the PMU does not set the SIER TYPE field, so it remains zero. > As a result, valid continuous samples were incorrectly > treated as invalid and dropped. Fixed this by gating the > SIER TYPE validation with mark_event, so the check runs only > for marked (random) events. Continuous samples now skip this > check and are recorded normally in the final data recording path. >=20 > Fixes: 2ffb26afa642 ("arch/powerpc/perf: Check the instruction type = before creating sample with perf_mem_data_src") > Signed-off-by: Shivani Nittor The changes looks good to me. Reviewed-by : Athira Rajeev > Thanks Athira > --- >=20 > arch/powerpc/perf/core-book3s.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/powerpc/perf/core-book3s.c = b/arch/powerpc/perf/core-book3s.c > index 8b0081441f85..2e6adf5b95c4 100644 > --- a/arch/powerpc/perf/core-book3s.c > +++ b/arch/powerpc/perf/core-book3s.c > @@ -2242,6 +2242,7 @@ static void record_and_restart(struct perf_event = *event, unsigned long val, > const u64 last_period =3D event->hw.last_period; > s64 prev, delta, left; > int record =3D 0; > + int mark_event =3D regs->dsisr & MMCRA_SAMPLE_ENABLE; >=20 > if (event->hw.state & PERF_HES_STOPPED) { > write_pmc(event->hw.idx, 0); > @@ -2304,9 +2305,9 @@ static void record_and_restart(struct perf_event = *event, unsigned long val, > * In ISA v3.0 and before values "0" and "7" are considered reserved. > * In ISA v3.1, value "7" has been used to indicate "larx/stcx". > * Drop the sample if "type" has reserved values for this field with a > - * ISA version check. > + * ISA version check for marked events. > */ > - if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && > + if (mark_event && event->attr.sample_type & PERF_SAMPLE_DATA_SRC && > ppmu->get_mem_data_src) { > val =3D (regs->dar & SIER_TYPE_MASK) >> SIER_TYPE_SHIFT; > if (val =3D=3D 0 || (val =3D=3D 7 && = !cpu_has_feature(CPU_FTR_ARCH_31))) { > --=20 > 2.47.3 >=20