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Mon, 16 Dec 2024 10:02:26 +0000 (GMT) Content-Type: text/plain; charset=utf-8 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3818.100.11.1.3\)) Subject: Re: [PATCH] tools/perf/arch/powerpc: Add register mask for power11 PVR in extended regs From: Athira Rajeev In-Reply-To: <2907ca2f-b973-42fd-ae03-99732dfda7a1@linux.ibm.com> Date: Mon, 16 Dec 2024 15:32:12 +0530 Cc: acme@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, irogers@google.com, namhyung@kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, maddy@linux.ibm.com, disgoel@linux.vnet.ibm.com, hbathini@linux.ibm.com Content-Transfer-Encoding: quoted-printable Message-Id: <0402AAF0-5498-48C7-BEBA-2C0B7508D9E2@linux.vnet.ibm.com> References: <20241206135637.36166-1-atrajeev@linux.vnet.ibm.com> <2907ca2f-b973-42fd-ae03-99732dfda7a1@linux.ibm.com> To: kajoljain , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers X-Mailer: Apple Mail (2.3818.100.11.1.3) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: r-IvdmR-sjJKaBbc_LpFv8jeup8W4K4o X-Proofpoint-GUID: pkGSb33H05pQcJrbwsQWXg2E2tI0LIeF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412160083 > On 11 Dec 2024, at 5:32=E2=80=AFPM, kajoljain = wrote: >=20 >=20 >=20 > On 12/6/24 19:26, Athira Rajeev wrote: >> Perf tools side uses extended mask to display the platform >> supported register names (with -I? option) to the user >> and also send this mask to the kernel to capture the extended = registers >> as part of each sample. This mask value is decided based on >> the processor version ( from PVR ). >>=20 >> Add PVR value for power11 to enable capturing the extended regs >> as part of sample in power11. >=20 > Patch looks fine to me. >=20 > Reviewed-by: Kajol Jain Hi Can we please pull in this patch if it looks fine. Thanks Athira >=20 >=20 >>=20 >> Signed-off-by: Athira Rajeev >> --- >>=20 >> tools/perf/arch/powerpc/util/perf_regs.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >>=20 >> diff --git a/tools/perf/arch/powerpc/util/perf_regs.c = b/tools/perf/arch/powerpc/util/perf_regs.c >> index e8e6e6fc6f17..bd36cfd420a2 100644 >> --- a/tools/perf/arch/powerpc/util/perf_regs.c >> +++ b/tools/perf/arch/powerpc/util/perf_regs.c >> @@ -16,6 +16,7 @@ >>=20 >> #define PVR_POWER9 0x004E >> #define PVR_POWER10 0x0080 >> +#define PVR_POWER11 0x0082 >>=20 >> static const struct sample_reg sample_reg_masks[] =3D { >> SMPL_REG(r0, PERF_REG_POWERPC_R0), >> @@ -207,7 +208,7 @@ uint64_t arch__intr_reg_mask(void) >> version =3D (((mfspr(SPRN_PVR)) >> 16) & 0xFFFF); >> if (version =3D=3D PVR_POWER9) >> extended_mask =3D PERF_REG_PMU_MASK_300; >> - else if (version =3D=3D PVR_POWER10) >> + else if ((version =3D=3D PVR_POWER10) || (version =3D=3D = PVR_POWER11)) >> extended_mask =3D PERF_REG_PMU_MASK_31; >> else >> return mask; >=20