From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from relay3.mail.twtelecom.net (relay3.mail.twtelecom.net [216.136.95.10]) by ozlabs.org (Postfix) with ESMTP id 40A9267A6C for ; Tue, 26 Apr 2005 07:27:49 +1000 (EST) Received: from Spaceballs (66-194-80-47.gen.twtelecom.net [66.194.80.47]) by relay3.mail.twtelecom.net (Postfix) with ESMTP id 8EFB24AC3 for ; Mon, 25 Apr 2005 16:10:37 -0500 (CDT) From: "Stuart Yoder" To: Date: Mon, 25 Apr 2005 16:10:28 -0500 Message-ID: <052201c549db$37e8b430$2f010a0a@foundation.com> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0523_01C549B1.4F12AC30" Subject: PowerPC + SMP List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. ------=_NextPart_000_0523_01C549B1.4F12AC30 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi. I am trying to figure out where in the PowerPC kernel the HID1 register is updated to enable bits dealing with cache coherency in an SMP system. Grepping through the arch/ppc source does not reveal much. I have two 7447A processors and somewhere the ABE and SYNCBE bits in HID1 need to be turned on to enable cache coherency. Is supposed to happen in the bootloader prior to the kernel running?? Thanks, Stuart Yoder ------=_NextPart_000_0523_01C549B1.4F12AC30 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message
Hi.
 
I am = trying to=20 figure out where in the PowerPC kernel the HID1 register is updated to = enable=20 bits dealing with cache coherency in an SMP system.   Grepping = through=20 the arch/ppc source does not reveal much.
 
I = have two=20 7447A processors and somewhere the ABE and SYNCBE bits in HID1 need = to be=20 turned on to enable cache coherency.   Is supposed to happen = in the=20 bootloader prior to the kernel running??
 
Thanks,
Stuart = Yoder
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