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From: "Stuart Yoder" <stuart.yoder@conformative.com>
To: <linuxppc-dev@ozlabs.org>
Subject: PowerPC + SMP
Date: Mon, 25 Apr 2005 16:11:08 -0500	[thread overview]
Message-ID: <052701c549db$4fb20760$2f010a0a@foundation.com> (raw)

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Hi.
 
I am trying to figure out where in the PowerPC kernel the HID1 register
is updated to enable bits dealing with cache coherency in an SMP system.
Grepping through the arch/ppc source does not reveal much.
 
I have two 7447A processors and somewhere the ABE and SYNCBE bits need
to be turned on to enable cache coherency.   Is supposed to happen in
the bootloader prior to the kernel running??
 
Thanks,
Stuart Yoder

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             reply	other threads:[~2005-04-25 21:44 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-04-25 21:11 Stuart Yoder [this message]
2005-04-26  3:36 ` PowerPC + SMP Benjamin Herrenschmidt
2005-04-26 14:54   ` Stuart Yoder
2005-04-26 17:35     ` Wolfgang Denk
2005-04-26 19:07       ` Stuart Yoder
2005-04-26 22:27     ` Benjamin Herrenschmidt
2005-04-26 23:04     ` Paul Mackerras
  -- strict thread matches above, loose matches on Subject: below --
2005-04-27  4:37 Frank
2005-04-25 21:10 Stuart Yoder
2005-04-25 21:39 ` Kumar Gala
2005-04-26 19:16   ` Stuart Yoder
2005-04-26 19:23     ` Kumar Gala

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