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From: "Stuart Yoder" <stuart.yoder@conformative.com>
To: "'linuxppc-dev list'" <linuxppc-dev@ozlabs.org>
Date: Tue, 26 Apr 2005 09:54:10 -0500
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Subject: RE: PowerPC + SMP
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Thanks Ben.

That raises a question though-- how can I know what assumptions the
kernel makes about the state of the CPU/system when it begins execution?
Is this clearly documented anywhere?

I am using U-boot on my SMP system and U-boot is not SMP aware.  Do you
know of other open source bootloaders for Linux that would set up the
CPUs as the kernel expects.

Thanks,
Stuart Yoder


> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org] 
> Sent: Monday, April 25, 2005 10:37 PM
> To: Stuart Yoder
> Cc: linuxppc-dev list
> Subject: Re: PowerPC + SMP
> 
> 
> On Mon, 2005-04-25 at 16:11 -0500, Stuart Yoder wrote:
> > Hi.
> >  
> > I am trying to figure out where in the PowerPC kernel the HID1 
> > register is updated to enable bits dealing with cache 
> coherency in an
> > SMP system.   Grepping through the arch/ppc source does not reveal
> > much.
> >  
> > I have two 7447A processors and somewhere the ABE and 
> SYNCBE bits need
> > to be turned on to enable cache coherency.   Is supposed to 
> happen in
> > the bootloader prior to the kernel running??
> 
> It's usually expected to happen in the firmware yes, though 
> the kernel does some of it's own 'fixups' (look at setup_cpu_6xx.S)
> 
> Ben.
> 
> 
> 
> 
>